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Pooi See Lee - IEEE Xplore Author Profile

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Chemiresistors of varying Copper Phthalocyanine sensing layer thickness, from 10 to 350 nm, have been fabricated and tested for sensing to sub-ppm levels of Nitrogen Dioxide. The results obtained were analyzed and the kinetics was shown to correlate well with first order kinetics, rather than with Elovich model. In explaining the sensitivity trend to thickness variation, gas diffusion into the lay...Show More
Multilevel high-resistance states are achieved in TiN/HfOx/Pt resistive switching random access memory device by controlling the reset stop voltage. Impedance spectroscopy is used to study the multilevel high-resistance states. It is shown that the high-resistance states can be described with an equivalent circuit consisting of the major components R_{s} , R , and C corresponding to the ...Show More
In this paper, we report a gas flow phenomenon induced by ultrasonic water cavitation and capillary wave in a vibrating hollow tip and reflector system. The cavitation clouds generated a gas suction force and the capillary wave created tunnels through which the gas could go into the liquid. The gas flow rate was measured and compared under different conditions, including applied power, type of ref...Show More
This paper illustrates the novel approaches to augment the sensing behavior of In2O3 base nanowires towards pollutant gases using nanowire field effect transistors (NWFETs). One of the approaches is based on the method of doping. Zn-doping increases the oxygen vacancies which enhance the oxygen ion adsorption on the nanowire surface. The resultant indium zinc oxide (IZO) nanowires show a good sele...Show More
We have fabricated silicon nanowire N-MOSFETs using erbium disilicide (ErSi2-x) in a Schottky source/drain back-gated architecture. Although the subthreshold swing (~180 mV/dec) and drain-induced barrier lowering (~500 mV/V) are high due thick BOX as gate oxide, the fabricated Schottky transistors show acceptable drive current ~900 muA/mum and high Ion/Ioff ratio (~105). This is attributed to the ...Show More
We demonstrate high-performance Schottky CMOS transistors with NiSi source/drain and gate-all-around (GAA) silicon nanowire (~5 nm) channels. The transistors exhibit good I on/I off characteristics, along with fully controlled shortchannel effects revealed by low drain-induced barrier lowering (~10 mV/V) and near-ideal subthreshold swing (~60 mV/dec). Although the N-MOSFET required dopant segregat...Show More
Summary form only given. Carbon nanotubes (CNTs) have attracted much attention in sensor applications because they are highly sensitive to molecular adsorption on the tube wall or within the tubes. The random networks of CNTs can be easily produced either by direct growth on a catalyzed substrate or by deposition onto a substrate from a carbon nanotube suspension, and their electrical properties a...Show More
The integration of copper (Cu) and low-k dielectrics has posed challenges for stress migration (SM) reliability. Besides process tuning, design for manufacturability (DFM) approach is proposed to suppress stress-induced void failures. In this paper, a three-dimensional (3D) finite element analysis (FEA) simulation model was used to identify the main mechanisms of several key processes and design a...Show More
Effect of Ti alloying during both RTA and LTA on Ni silicide formation is studied. In the RTA annealed samples, Ni3Si2 was found to be the first silicide formed at 600degC and stable up to 900degC. On the other hand, unique triple layer microstructures were found in the sample after single-pulsed LTA at high laser fluence. Ti rapidly segregates from the alloy melt and forms a protective TiOx overl...Show More
Fabrication of ferroelectric memory field effect transistor (FEMFET) is presented with copolymer P(VDF-TrFE) as gate dielectric. Spin-coated copolymer film has semi-crystalline structure after annealing, in which the crystallites contains ferroelectric and paraelectric phase. Dipolar alignment in ferroelectric phase is controlled with the sweeping of transistor gate bias. Ferroelectric remanent po...Show More
Formation of Co-silicide contact layers on narrow silicon regions using multiple-pulse excimer laser annealing is demonstrated. Excellent performance of junction leakage behavior can be attained on narrow-width n/sup +//p and p/sup +//n junction as compared with standard rapid thermal annealed samples. Liquid-phase epitaxial Co-silicide regrowth has been found to occur and create a smooth and abru...Show More
Erbium silicide Schottky diodes formed on Si(001) substrate using rapid thermal annealing method show degraded Schottky-barrier height /spl phi//sub Beff/ and ideality factor n due to the presence of silicide-induced microstructural defects which are likely sources of trap states. A method to improve the /spl phi//sub Beff/ and n of the diodes utilizing in situ Ar plasma cleaning to induce a light...Show More
A novel salicide technology to improve the thermal stability of the conventional Ni silicide has been developed by employing Ni(Pt) alloy salicidation. This technique provides an effective avenue to overcome the low thermal budget (<700/spl deg/C) of the conventional Ni salicidation by forming Ni(Pt)Si. The addition of Pt has enhanced the thermal stability of NiSi. Improved sheet resistance of the...Show More
An improved Ni salicide process has been developed by incorporating nitrogen (N/sub 2//sup +/) implant prior to Ni deposition to widen the salicide processing temperature window. Salicided poly-Si gate and active regions of different linewidths show improved thermal stability with low sheet resistance up to a salicidation temperature of 700 and 750/spl deg/C, respectively. Nitrogen was found to be...Show More