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Bipin Rajendran

Also published under: B. Rajendran

Publications
81
Citations
3,120
Publications by Year
20072025
Co-Authors:
Show All Co-Authors (165)
Image of author Bipin Rajendran

Bipin Rajendran

Also published under: B. Rajendran

Affiliation

Department of Engineering
Centre for Intelligent Information Processing Systems (CIIPS)
King’s College London, London, U.K.

Publication Topics

Biography

Bipin Rajendran (bipin@njit.edu) received his B.Tech. degree in instrumentation from the Indian Institute of Technology Kharagpur in 2000 and his M.S. and Ph.D. degrees in electrical engineering from Stanford University, California, in 2003 and 2006, respectively. He is an associate professor of electrical and computer engineering at the New Jersey Institute of Technology. He was a master inventor and research staff member at the IBM T.J. Watson Research Center, New York, from 2006 to 2012 and a faculty member in the Electrical Engineering Department, the Indian Institute of Technology Bombay, from 2012 to 2015. His research focuses on building scalable architectures and systems for neuromorphic computing using nanoscale devices. He has aut...
Publications
81
Citations
3,120
Publications by Year
20072025
Co-Authors:
Show All Co-Authors (165)
Author's Published Works

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Bayes2IMC: In-Memory Computing for Bayesian Binary Neural Networks

Prabodh Katti;Clement Ruah;Osvaldo Simeone;Bashir M. Al-Hashimi;Bipin Rajendran

IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2025 | Early Access Article |
Bayesian Neural Networks (BNNs) generate an ensemble of possible models by treating model weights as random variables. This enables them to provide superior estimates of decision uncertainty. However, implementing Bayesian inference in hardware is resource-intensive, as it requires noise sources to generate the desired model weights. In this work, we introduce Bayes2IMC, an in-memory computing (IM...Show More

Bayes2IMC: In-Memory Computing for Bayesian Binary Neural Networks

Prabodh Katti;Clement Ruah;Osvaldo Simeone;Bashir M. Al-Hashimi;Bipin Rajendran

Year: 2025 | Early Access Article |

Baseline Drift Tolerant Signal Encoding for ECG Classification with Deep Learning

Robert O’Shea;Prabodh Katti;Bipin Rajendran

2024 46th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)
Year: 2024 | Conference Paper |
Common artefacts such as baseline drift, rescaling, and noise critically limit the performance of machine learning-based automated ECG analysis and interpretation. This study proposes Derived Peak (DP) encoding, a non-parametric method that generates signed spikes corresponding to zero crossings of the signal’s first and second-order time derivatives. Notably, DP encoding is invariant to shift and...Show More

Baseline Drift Tolerant Signal Encoding for ECG Classification with Deep Learning

Robert O’Shea;Prabodh Katti;Bipin Rajendran

Year: 2024 | Conference Paper |

Hardware-Software Co-optimised Fast and Accurate Deep Reconfigurable Spiking Inference Accelerator Architecture Design Methodology

Anagha Nimbekar;Prabodh Katti;Chen Li;Bashir M. Al-Hashimi;Amit Acharyya;Bipin Rajendran

2024 IEEE 37th International System-on-Chip Conference (SOCC)
Year: 2024 | Conference Paper |
Spiking Neural Networks (SNNs) have emerged as a promising approach to improve the energy efficiency of machine learning models, as they naturally implement event-driven computations while avoiding expensive multiplication operations.In this paper, we develop a hardware-software co-optimisation strategy to port software-trained deep neural networks (DNN) to reduced-precision spiking models demonst...Show More

Hardware-Software Co-optimised Fast and Accurate Deep Reconfigurable Spiking Inference Accelerator Architecture Design Methodology

Anagha Nimbekar;Prabodh Katti;Chen Li;Bashir M. Al-Hashimi;Amit Acharyya;Bipin Rajendran

Year: 2024 | Conference Paper |

Neuromorphic In-Context Learning for Energy-Efficient MIMO Symbol Detection

Zihang Song;Osvaldo Simeone;Bipin Rajendran

2024 IEEE 25th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC)
Year: 2024 | Conference Paper |
In-context learning (ICL), a property demonstrated by transformer-based sequence models, refers to the automatic inference of an input-output mapping based on examples of the mapping provided as context. ICL requires no explicit learning, i.e., no explicit updates of model weights, directly mapping context and new input to the new output. Prior work has proved the usefulness of ICL for detection i...Show More

Neuromorphic In-Context Learning for Energy-Efficient MIMO Symbol Detection

Zihang Song;Osvaldo Simeone;Bipin Rajendran

Year: 2024 | Conference Paper |

Stochastic Spiking Attention: Accelerating Attention with Stochastic Computing in Spiking Networks

Zihang Song;Prabodh Katti;Osvaldo Simeone;Bipin Rajendran

2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)
Year: 2024 | Conference Paper |
Cited by: Papers (1)
Spiking Neural Networks (SNNs) have been recently integrated into Transformer architectures due to their potential to reduce computational demands and to improve power efficiency. Yet, the implementation of the attention mechanism using spiking signals on general-purpose computing platforms remains ineffi-cient. In this paper, we propose a novel framework leveraging stochastic computing (SC) to ef...Show More

Stochastic Spiking Attention: Accelerating Attention with Stochastic Computing in Spiking Networks

Zihang Song;Prabodh Katti;Osvaldo Simeone;Bipin Rajendran

Year: 2024 | Conference Paper |

Bayesian Inference Accelerator for Spiking Neural Networks

Prabodh Katti;Anagha Nimbekar;Chen Li;Amit Acharyya;Bashir M. Al-Hashimi;Bipin Rajendran

2024 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2024 | Conference Paper |
Bayesian neural networks offer better estimates of model uncertainty compared to frequentist networks. However, inference involving Bayesian models requires multiple instantiations or sampling of the network parameters, requiring significant computational resources. Compared to traditional deep learning networks, spiking neural networks (SNNs) have the potential to reduce computational area and po...Show More

Bayesian Inference Accelerator for Spiking Neural Networks

Prabodh Katti;Anagha Nimbekar;Chen Li;Amit Acharyya;Bashir M. Al-Hashimi;Bipin Rajendran

Year: 2024 | Conference Paper |

Energy-Efficient on-Board Radio Resource Management for Satellite Communications via Neuromorphic Computing

Flor Ortiz;Nicolas Skatchkovsky;Eva Lagunas;Wallace A. Martins;Geoffrey Eappen;Saed Daoud;Osvaldo Simeone;Bipin Rajendran;Symeon Chatzinotas

IEEE Transactions on Machine Learning in Communications and Networking
Year: 2024 | Volume: 2 | Journal Article |
Cited by: Papers (3)
The latest Satellite Communication (SatCom) missions are characterized by a fully reconfigurable on-board software-defined payload, capable of adapting radio resources to the temporal and spatial variations of the system traffic. As pure optimization-based solutions have shown to be computationally tedious and to lack flexibility, Machine Learning (ML)-based methods have emerged as promising alter...Show More

Energy-Efficient on-Board Radio Resource Management for Satellite Communications via Neuromorphic Computing

Flor Ortiz;Nicolas Skatchkovsky;Eva Lagunas;Wallace A. Martins;Geoffrey Eappen;Saed Daoud;Osvaldo Simeone;Bipin Rajendran;Symeon Chatzinotas

Year: 2024 | Volume: 2 | Journal Article |

Bayesian Inference on Binary Spiking Networks Leveraging Nanoscale Device Stochasticity

Prabodh Katti;Nicolas Skatchkovsky;Osvaldo Simeone;Bipin Rajendran;Bashir M. Al-Hashimi

2023 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2023 | Conference Paper |
Cited by: Papers (1)
Bayesian Neural Networks (BNNs) can overcome the problem of overconfidence that plagues traditional frequentist deep neural networks, and are hence considered to be a key enabler for reliable AI systems. However, conventional hardware realizations of BNNs are resource intensive, requiring the imple-mentation of random number generators for synaptic sampling. Owing to their inherent stochasticity d...Show More

Bayesian Inference on Binary Spiking Networks Leveraging Nanoscale Device Stochasticity

Prabodh Katti;Nicolas Skatchkovsky;Osvaldo Simeone;Bipin Rajendran;Bashir M. Al-Hashimi

Year: 2023 | Conference Paper |

A Convolutional Spiking Network for Gesture Recognition in Brain-Computer Interfaces

Yiming Ai;Bipin Rajendran

2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)
Year: 2023 | Conference Paper |
Cited by: Papers (2)
Brain-computer interfaces are being explored for a wide variety of therapeutic applications. Typically, this involves measuring and analyzing continuous-time electrical brain activity via techniques such as electrocorticogram (ECoG) or electroencephalography (EEG) to drive external devices. However, due to the inherent noise and variability in the measurements, the analysis of these signals is cha...Show More

A Convolutional Spiking Network for Gesture Recognition in Brain-Computer Interfaces

Yiming Ai;Bipin Rajendran

Year: 2023 | Conference Paper |

Neuromorphic Accelerator for Deep Spiking Neural Networks with NVM Crossbar Arrays

Shruti R. Kulkarni;Shihui Yin;Jae-sun Seo;Bipin Rajendran

2022 IEEE International Conference on Emerging Electronics (ICEE)
Year: 2022 | Conference Paper |
In this paper, we present a scalable digital hardware accelerator based on non-volatile memory arrays capable of realizing deep convolutional spiking neural networks (SNNs). Our design studies are conducted using a compact model for spin-transfer torque random access memory (STT-RAM) devices. Large networks are realized by tiling multiple cores which communicate by transmitting spike packets via a...Show More

Neuromorphic Accelerator for Deep Spiking Neural Networks with NVM Crossbar Arrays

Shruti R. Kulkarni;Shihui Yin;Jae-sun Seo;Bipin Rajendran

Year: 2022 | Conference Paper |

Spiking Generative Adversarial Networks With a Neural Network Discriminator: Local Training, Bayesian Models, and Continual Meta-Learning

Bleema Rosenfeld;Osvaldo Simeone;Bipin Rajendran

IEEE Transactions on Computers
Year: 2022 | Volume: 71, Issue: 11 | Journal Article |
Cited by: Papers (14)
Neuromorphic data carries information in spatio-temporal patterns encoded by spikes. Accordingly, a central problem in neuromorphic computing is training spiking neural networks (SNNs) to reproduce spatio-temporal spiking patterns in response to given spiking stimuli. Most existing approaches model the input-output behavior of an SNN in a deterministic fashion by assigning each input to a specific...Show More

Spiking Generative Adversarial Networks With a Neural Network Discriminator: Local Training, Bayesian Models, and Continual Meta-Learning

Bleema Rosenfeld;Osvaldo Simeone;Bipin Rajendran

Year: 2022 | Volume: 71, Issue: 11 | Journal Article |

Fast On-Device Adaptation for Spiking Neural Networks Via Online-Within-Online Meta-Learning

Bleema Rosenfeld;Bipin Rajendran;Osvaldo Simeone

2021 IEEE Data Science and Learning Workshop (DSLW)
Year: 2021 | Conference Paper |
Cited by: Papers (4)
Spiking Neural Networks (SNNs) have recently gained popularity as machine learning models for on-device edge intelligence for applications such as mobile healthcare management and natural language processing due to their low power profile. In such highly personalized use cases, it is important for the model to be able to adapt to the unique features of an individual with only a minimal amount of t...Show More

Fast On-Device Adaptation for Spiking Neural Networks Via Online-Within-Online Meta-Learning

Bleema Rosenfeld;Bipin Rajendran;Osvaldo Simeone

Year: 2021 | Conference Paper |

Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks

Vinay Joshi;Wangxin He;Jae-sun Seo;Bipin Rajendran

2021 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2021 | Conference Paper |
The cost involved in training deep neural networks (DNNs) on von-Neumann architectures has motivated the development of novel solutions for efficient DNN training accelerators. We propose a hybrid in-memory computing (HIC) architecture for the training of DNNs on hardware accelerators that results in memory-efficient inference and outperforms baseline software accuracy in benchmark tasks. We intro...Show More

Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks

Vinay Joshi;Wangxin He;Jae-sun Seo;Bipin Rajendran

Year: 2021 | Conference Paper |

ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning

Vinay Joshi;Geethan Karunaratne;Manuel Le Gallo;Irem Boybat;Christophe Piveteau;Abu Sebastian;Bipin Rajendran;Evangelos Eleftheriou

2020 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2020 | Conference Paper |
Cited by: Papers (1)
Deep neural networks (DNNs) have surpassed human-level accuracy in a variety of cognitive tasks but at the cost of significant memory/time requirements in DNN training. This limits their deployment in energy and memory limited applications that require real-time learning. Matrix-vector multiplications (MVM) and vector-vector outer product (VVOP) are the two most expensive operations associated wit...Show More

ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning

Vinay Joshi;Geethan Karunaratne;Manuel Le Gallo;Irem Boybat;Christophe Piveteau;Abu Sebastian;Bipin Rajendran;Evangelos Eleftheriou

Year: 2020 | Conference Paper |

An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays

Shruti R. Kulkarni;Shihui Yin;Jae-sun Seo;Bipin Rajendran

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Year: 2020 | Conference Paper |
Cited by: Papers (4)
In this work, we present a scheme for implementing learning on a digital non-volatile memory (NVM) based hardware accelerator for Spiking Neural Networks (SNNs). Our design estimates across three prominent non-volatile memories - Phase Change Memory (PCM), Resistive RAM (RRAM), and Spin Transfer Torque RAM (STT-RAM) show that the STT-RAM arrays enable at least 2× higher throughput compared to the ...Show More

An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays

Shruti R. Kulkarni;Shihui Yin;Jae-sun Seo;Bipin Rajendran

Year: 2020 | Conference Paper |

Kinetic Monte Carlo Simulation of Interface-Controlled Hafnia-Based Resistive Memory

Xu Xu;Bipin Rajendran;M. P. Anantram

IEEE Transactions on Electron Devices
Year: 2020 | Volume: 67, Issue: 1 | Journal Article |
Cited by: Papers (13)
Kinetic Monte Carlo simulations of resistive memory devices have been performed by paying attention to the vacancy-interstitial generation near the Hafnia-metal electrode interface. In our model, an oxygen vacancy is generated in Hafnia near the interface, with the corresponding oxygen atom residing in the metal electrode. These oxygen atoms form a thin insulating oxide layer at the Hafnia-active ...Show More

Kinetic Monte Carlo Simulation of Interface-Controlled Hafnia-Based Resistive Memory

Xu Xu;Bipin Rajendran;M. P. Anantram

Year: 2020 | Volume: 67, Issue: 1 | Journal Article |

Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays

Shruti R. Kulkarni;Deepak Vinayak Kadetotad;Shihui Yin;Jae-Sun Seo;Bipin Rajendran

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Year: 2019 | Conference Paper |
Cited by: Papers (9)
In this paper, we propose a Spin Transfer Torque RAM (STT-RAM) based neurosynaptic core to implement a hardware accelerator for Spiking Neural Networks (SNNs), which mimic the time-based signal encoding and processing mechanisms of the human brain. The computational core consists of a crossbar array of non-volatile STT-RAMs, read/write peripheral circuits, and digital logic for the spiking neurons...Show More

Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays

Shruti R. Kulkarni;Deepak Vinayak Kadetotad;Shihui Yin;Jae-Sun Seo;Bipin Rajendran

Year: 2019 | Conference Paper |

Phase-Change Memory Models for Deep Learning Training and Inference

S. R. Nandakumar;Irem Boybat;Vinay Joshi;Christophe Piveteau;Manuel Le Gallo;Bipin Rajendran;Abu Sebastian;Evangelos Eleftheriou

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Year: 2019 | Conference Paper |
Cited by: Papers (14)
Non-volatile analog memory devices such as phase-change memory (PCM) enable designing dedicated connectivity matrices for the hardware implementation of deep neural networks (DNN). In this in-memory computing approach, the analog conductance states of the memory device can be gradually updated to train DNNs on-chip or software trained connection strengths may be programmed one-time to the devices ...Show More

Phase-Change Memory Models for Deep Learning Training and Inference

S. R. Nandakumar;Irem Boybat;Vinay Joshi;Christophe Piveteau;Manuel Le Gallo;Bipin Rajendran;Abu Sebastian;Evangelos Eleftheriou

Year: 2019 | Conference Paper |

Low-Power Neuromorphic Hardware for Signal Processing Applications: A Review of Architectural and System-Level Design Approaches

Bipin Rajendran;Abu Sebastian;Michael Schmuker;Narayan Srinivasa;Evangelos Eleftheriou

IEEE Signal Processing Magazine
Year: 2019 | Volume: 36, Issue: 6 | Magazine Article |
Cited by: Papers (110)
Machine learning has emerged as the dominant tool for implementing complex cognitive tasks that require supervised, unsupervised, and reinforcement learning. While the resulting machines have demonstrated in some cases even superhuman performance, their energy consumption has often proved to be prohibitive in the absence of costly supercomputers. Most state-of-the-art machine-learning solutions ar...Show More

Low-Power Neuromorphic Hardware for Signal Processing Applications: A Review of Architectural and System-Level Design Approaches

Bipin Rajendran;Abu Sebastian;Michael Schmuker;Narayan Srinivasa;Evangelos Eleftheriou

Year: 2019 | Volume: 36, Issue: 6 | Magazine Article |

Learning First-to-Spike Policies for Neuromorphic Control Using Policy Gradients

Bleema Rosenfeld;Osvaldo Simeone;Bipin Rajendran

2019 IEEE 20th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC)
Year: 2019 | Conference Paper |
Cited by: Papers (11)
Artificial Neural Networks (ANNs) are currently being used as function approximators in many state-of-the-art Reinforcement Learning (RL) algorithms. Spiking Neural Networks (SNNs) have been shown to drastically reduce the energy consumption of ANNs by encoding information in sparse temporal binary spike streams, hence emulating the communication mechanism of biological neurons. Due to their low e...Show More

Learning First-to-Spike Policies for Neuromorphic Control Using Policy Gradients

Bleema Rosenfeld;Osvaldo Simeone;Bipin Rajendran

Year: 2019 | Conference Paper |

Computational memory-based inference and training of deep neural networks

A. Sebastian;I. Boybat;M. Dazzi;I. Giannopoulos;V. Jonnalagadda;V. Joshi;G. Karunaratne;B. Kersting;R. Khaddam-Aljameh;S. R. Nandakumar;A. Petropoulos;C. Piveteau;T. Antonakopoulos;B. Rajendran;M. Le Gallo;E. Eleftheriou

2019 Symposium on VLSI Circuits
Year: 2019 | Conference Paper |
Cited by: Papers (2)
In-memory computing is an emerging computing paradigm where certain computational tasks are performed in place in a computational memory unit by exploiting the physical attributes of the memory devices. Here, we present an overview of the application of in-memory computing in deep learning, a branch of machine learning that has significantly contributed to the recent explosive growth in artificial...Show More

Computational memory-based inference and training of deep neural networks

A. Sebastian;I. Boybat;M. Dazzi;I. Giannopoulos;V. Jonnalagadda;V. Joshi;G. Karunaratne;B. Kersting;R. Khaddam-Aljameh;S. R. Nandakumar;A. Petropoulos;C. Piveteau;T. Antonakopoulos;B. Rajendran;M. Le Gallo;E. Eleftheriou

Year: 2019 | Conference Paper |

Computational memory-based inference and training of deep neural networks

A. Sebastian;I. Boybat;M. Dazzi;I. Giannopoulos;V. Jonnalagadda;V. Joshi;G. Karunaratne;B. Kersting;R. Khaddam-Aljameh;S. R. Nandakumar;A. Petropoulos;C. Piveteau;T. Antonakopoulos;B. Rajendran;M. Le Gallo;E. Eleftheriou

2019 Symposium on VLSI Technology
Year: 2019 | Conference Paper |
Cited by: Papers (26)
In-memory computing is an emerging computing paradigm where certain computational tasks are performed in place in a computational memory unit by exploiting the physical attributes of the memory devices. Here, we present an overview of the application of in-memory computing in deep learning, a branch of machine learning that has significantly contributed to the recent explosive growth in artificial...Show More

Computational memory-based inference and training of deep neural networks

A. Sebastian;I. Boybat;M. Dazzi;I. Giannopoulos;V. Jonnalagadda;V. Joshi;G. Karunaratne;B. Kersting;R. Khaddam-Aljameh;S. R. Nandakumar;A. Petropoulos;C. Piveteau;T. Antonakopoulos;B. Rajendran;M. Le Gallo;E. Eleftheriou

Year: 2019 | Conference Paper |

Building Next-Generation AI systems: Co-Optimization of Algorithms, Architectures, and Nanoscale Memristive Devices

Bipin Rajendran;Abu Sebastian;Evangelos Eleftheriou

2019 IEEE 11th International Memory Workshop (IMW)
Year: 2019 | Conference Paper |
Cited by: Papers (1)
Computing systems inspired by the architecture of the human brain is poised to revolutionize the engines for information processing and data analytics. However, the efficiency and performance of these platforms pale in comparison with the human brain, especially when benchmarked in terms of metrics such as intelligence per Watt per square mm. In this paper, we review some recent progress and futur...Show More

Building Next-Generation AI systems: Co-Optimization of Algorithms, Architectures, and Nanoscale Memristive Devices

Bipin Rajendran;Abu Sebastian;Evangelos Eleftheriou

Year: 2019 | Conference Paper |

Impact of conductance drift on multi-PCM synaptic architectures

I. Boybat;S. R. Nandakumar;M. Le Gallo;B. Rajendran;Y. Leblebici;A. Sebastian;E. Eleftheriou

2018 Non-Volatile Memory Technology Symposium (NVMTS)
Year: 2018 | Conference Paper |
Cited by: Papers (9)
In-memory computing with nanoscale memristive devices such as phase-change memory (PCM) has emerged as an alternative to conventional von Neumann systems to train deep neural networks (DNN) where a synaptic weight is represented by the device conductance. However, PCM devices exhibit temporal evolution of the conductance values referred to as the conductance drift, which poses challenges for maint...Show More

Impact of conductance drift on multi-PCM synaptic architectures

I. Boybat;S. R. Nandakumar;M. Le Gallo;B. Rajendran;Y. Leblebici;A. Sebastian;E. Eleftheriou

Year: 2018 | Conference Paper |

Well-Posed Verilog-A Compact Model for Phase Change Memory

Shruti R. Kulkarni;Deepak Vinayak Kadetotad;Jae-sun Seo;Bipin Rajendran

2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
Year: 2018 | Conference Paper |
Cited by: Papers (2)
In this work, we demonstrate a well-posed compact model for phase change memory (PCM) devices based on Ge2 Sb2 Te5, (GST) chalcogenide. This model supports all modes of simulation including transient, DC, and AC. The model is developed in Verilog-A and simulated using HSPICE. It is computationally simple and successfully captures the key high level behaviors of memory switching, including the resi...Show More

Well-Posed Verilog-A Compact Model for Phase Change Memory

Shruti R. Kulkarni;Deepak Vinayak Kadetotad;Jae-sun Seo;Bipin Rajendran

Year: 2018 | Conference Paper |

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