Author details
Author's Published Works
Author details
Showing 1-18 of 18 results
- Sort
Filter Results
Show
Sort By
Results
The Role of Doping Technology in the CMOS Digital Revolution
2018 22nd International Conference on Ion Implantation Technology (IIT)
Year: 2018 | Conference Paper |
Cited by: Papers (1)
The last two decades have been marked by a digital revolution that has changed the use and exchange of information as never before. The late 20th century 250 nm node was a turning point in which the last remaining thermal diffusion steps for semiconductor doping were replaced by ion implantation. Inexpensive MP3 players and mobile phones appeared in the hands of common people around the globe at e...Show More
9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth
N. Klemmer;S. Akhtar;V. Srinivasan;P. Litmanen;H. Arora;S. Uppathil;S. Kaylor;A. Akour;V. Wang;M. Fares;F. Dulger;A. Frank;D. Ghosh;S. Madhavapeddi;H. Safiri;J. Mehta;A. Jain;H. Choo;E. Zhang;C. Sestok;C. Fernando;Rajagopal K.A.;S. Ramakrishnan;V. Sinari;V. Baireddy
2016 IEEE International Solid-State Circuits Conference (ISSCC)
Year: 2016 | Conference Paper |
9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth
N. Klemmer;S. Akhtar;V. Srinivasan;P. Litmanen;H. Arora;S. Uppathil;S. Kaylor;A. Akour;V. Wang;M. Fares;F. Dulger;A. Frank;D. Ghosh;S. Madhavapeddi;H. Safiri;J. Mehta;A. Jain;H. Choo;E. Zhang;C. Sestok;C. Fernando;Rajagopal K.A.;S. Ramakrishnan;V. Sinari;V. Baireddy
Year: 2016 | Conference Paper |
Selective Epitaxial Phosphorus-Doped SiGe Layers for Short-Channel Effect Reduction
Jeongwon Park;Ramachandran Balasubramanian;Amitabh Jain;Deborah Riley;Harpreet Juneja;Satheesh Kuppurao
2012 International Silicon-Germanium Technology and Device Meeting (ISTDM)
Year: 2012 | Conference Paper |
Cited by: Papers (1)
Epitaxially grown silicon germanium layers are utilized in very high performance short channel MOSFETs. To reduce short-channel effects, the substrate doping concentration must be increased at the edges of the source and drain. These regions commonly called halos are typically created by ion implantation but the precise positioning of the dopant is a challenge. As devices with embedded SiGe source...Show More
Reduced NiPtSi Schottky barriers by controlling interface composition and new materials incorporation
Christopher Hinkle;Jack Chan;Javier Mendez;Richard Chapman;Eric Vogel;Deborah Riley;Amitabh Jain;S. C. Song;K. Y. Lim;James Blatchford;Judy Shaw
2012 12th International Workshop on Junction Technology
Year: 2012 | Conference Paper |
Cited by: Papers (1)
Contact resistance (Rc) contributes over 65% of the total source to drain series resistance in <; 32 nm CMOS technologies. In this work, reduction of Rc is achieved by lowering the SBH through the incorporation of new materials into NiPtSi. The impact of implanted elemental species as well as alloyed low work function metals is discussed. As diffusion and subsequent interface composition is highly...Show More
Impact of laser spike annealing dwell time on wafer stress and photolithography overlay errors
Shrinivas Shetty;Amitabh Jain;David M. Owen;Jeffrey Mileham;Jeff Hebb;Yun Wang
2009 International Workshop on Junction Technology
Year: 2009 | Conference Paper |
The use of strained SiGe is essential to improvement in device performance. However, the structure is susceptible to strain relaxation and wafer deformation during thermal annealing. The accumulation of stress in the wafer needs to be controlled to minimize photolithographic overlay errors. Laser spike annealing offers negligible pattern effects, closed-loop temperature control, and localized heat...Show More
Wafer Temperature Measurement and Control During Laser Spike Annealing
Shaoyin Chen;Jeff Hebb;Amitabh Jain;Shrinivas Shetty;Yun Wang
2007 15th International Conference on Advanced Thermal Processing of Semiconductors
Year: 2007 | Conference Paper |
Sub-melt millisecond annealing technologies have been widely accepted for current and future IC fabrication. Real-time temperature control, both within wafer and from wafer-to-wafer, is one of the key challenges that must be addressed for the successful introduction of any millisecond annealing technology into a production environment. In this paper, we show results from a novel pyrometry approach...Show More
Transistor optimization for leakage power management in a 65 nm CMOS technology for wireless and mobile applications
S. Zhao;A. Chatterjee;S. Tang;J. Yoon;S. Crank;H. Bu;T. Houston;K. Sadra;A. Jain;Y. Wang;D. Redwine;Y. Chen;S. Siddiqui;G. Zhang;T. Laaksonen;C. Hall;S. Chang;L. Olsen;T. Riley;C. Meek;I. Hossain;J. Rosal;A. Tsao;J. Wu;D. Scott
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.
Year: 2004 | Conference Paper |
This paper presents a transistor optimization methodology tailored for wireless, digital consumer, and mobile applications that employ power management circuit techniques. This methodology is applied to a 65nm technology that supports a high-density (<0.5 um/sup 2/) embedded 6T SRAM cell. High performance logic (I/sub dn//I/sub dp/ = 550/300uA/um at L/sub poly/ = 39nm) and low leakage are achieved...Show More
Transistor optimization for leakage power management in a 65 nm CMOS technology for wireless and mobile applications
S. Zhao;A. Chatterjee;S. Tang;J. Yoon;S. Crank;H. Bu;T. Houston;K. Sadra;A. Jain;Y. Wang;D. Redwine;Y. Chen;S. Siddiqui;G. Zhang;T. Laaksonen;C. Hall;S. Chang;L. Olsen;T. Riley;C. Meek;I. Hossain;J. Rosal;A. Tsao;J. Wu;D. Scott
Year: 2004 | Conference Paper |
Modeling the effect of source/drain sidewall spacer process on boron ultra shallow junctions
S. Chakravarthi;P. Kohli;P.R. Chidambaram;H. Bu;A. Jain;B. Hornung;C.F. Machala
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.
Year: 2003 | Conference Paper |
A novel model is developed to explain the effect of the source/drain sidewall spacer process on boron drain extension formation. A diffusion model for hydrogen in the source/drain sidewall spacer is developed and combined with a model for boron diffusion in oxides. The model is first calibrated to hydrogen out-diffusion data from Nuclear Reaction Analysis (NRA) and then to boron diffusion data fro...Show More
Fluorine-assisted super-halo for sub-50-nm transistors
IEEE Electron Device Letters
Cited by: Papers (16)
The potential of using a fluorine-assisted super-halo for sub-50-nm transistors is analyzed for the first time. The capability of producing a super-sharp halo using fluorine is demonstrated by one-dimensional (1-D) SIMS profiles. The added ability to tailor the halo profile using fluorine for different transistor criteria on junction capacitance, tunneling current, V/sub t/ roll-off, and mobility ...Show More
Establishing advanced implant annealing for the 65 nm technology node
10th IEEE International Conference of Advanced Thermal Processing of Semiconductors
Year: 2002 | Conference Paper |
An essential requirement for the continued scaling of CMOS technology is the ability to fabricate junctions with decreased depth and increased abruptness without compromising the maximum activation level of dopants. Reduction of ion implantation energy has been instrumental in meeting this requirement and will play an important role in the future. However, advances in annealing technology continue...Show More
60 nm gate length dual-Vt CMOS for high performance applications
M. Mehrotra;J. Wu;A. Jain;T. Laaksonen;K. Kim;W. Bather;R. Koshy;J. Chen;J. Jacobs;V. Ukraintsev;L. Olsen;J. DeLoach;J. Mehigan;R. Agarwal;S. Walsh;D. Sekel;L. Tsung;M. Vaidyanathan;B. Trentman;K. Liu;S. Aur;R. Khamankar;P. Nicollian;Q. Jiang;Y. Xu;B. Campbell;P. Tiner;R. Wise;D. Scott;M. Rodder
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)
Year: 2002 | Conference Paper |
In this work, we present a 60 nm gate length CMOS for high performance applications at the 0.13 /spl mu/m CMOS node. The technology utilizes 193 nm gate lithography, dual spacers with thin spacer before drain extension implant and L-shaped nitride spacer after drain extensions, and remote-plasma nitrided dielectric with 1.75 nm EOT. 10-15% improvement in drive current is achieved with lower series...Show More
60 nm gate length dual-Vt CMOS for high performance applications
M. Mehrotra;J. Wu;A. Jain;T. Laaksonen;K. Kim;W. Bather;R. Koshy;J. Chen;J. Jacobs;V. Ukraintsev;L. Olsen;J. DeLoach;J. Mehigan;R. Agarwal;S. Walsh;D. Sekel;L. Tsung;M. Vaidyanathan;B. Trentman;K. Liu;S. Aur;R. Khamankar;P. Nicollian;Q. Jiang;Y. Xu;B. Campbell;P. Tiner;R. Wise;D. Scott;M. Rodder
Year: 2002 | Conference Paper |
Role of fluorine in low temperature dopant activation of boron
Proceedings of the Fourteenth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.01CH37197)
Year: 2001 | Conference Paper |
Summary form only given. MOS device scaling requires a decrease in lateral dimensions and in junction depths. Current projections call for junction depths in the 300 /spl Aring/ range in order to reduce short-channel effects of 0.07 /spl mu/m gate-length technologies. The key limiting factors in boron doped junctions are transient enhanced diffusion (TED) and the more recent concept of boron enhan...Show More
RTP for shallow junction formation-monitoring with repeatable, reliable sheet resistance measurements
2000 International Conference on Ion Implantation Technology Proceedings. Ion Implantation Technology - 2000 (Cat. No.00EX432)
Year: 2000 | Conference Paper |
Cited by: Papers (3)
RTP spike anneals are evaluated for various conditions of very low energy B implants. The effects of preamorphisation implant (PAI) and screen oxide on sheet resistance (Rs) are discussed. The implant profiles are analyzed using spreading resistance profiling (SRP), SIMS and 4-point probe measurements. By variation of the junction depth it is shown that the 4-point probes can affect the very shall...Show More
A 1.2V, sub-0.09 /spl mu/m gate length CMOS technology
M. Mehrotra;J.C. Hu;A. Jain;W. Shiau;V. Reddy;S. Aur;M. Rodder
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)
Year: 1999 | Conference Paper |
CMOS technology for 1.2 V high performance applications is being scaled to sub-0.09 /spl mu/m physical nominal gate lengths and with effective gate dielectric thickness less than 2 nm to achieve the roadmap trend for high performance applications. For this technology, formation of the gate dielectric is by remote-plasma nitridation. To support the short target gate length, pocket implants, reduced...Show More
The effect of deterministic spatial variations in retrograde well implants on shallow trench isolation for sub-0.18 /spl mu/m CMOS technology
D. Kapila;A. Jain;M. Nandakumar;S. Ashburn;K. Vasanth;S. Sridhar
The high energy retrograde well implants for sub-0.18 microns CMOS are done at a normal or near normal incidence to minimize the shadowing due to the thick photoresist edges. The endstation geometry in a high energy implanter results in an incident angle variation across the wafer, which causes strong spatial variations in the well profile and can negatively impact device performance. We show that...Show More
The effect of deterministic spatial variations in retrograde well implants on shallow trench isolation and latchup immunity
D. Kapila;A. Jain;M. Nandakumar;S. Ashburn;K. Vasanth;S. Sridhar
IWSM. 1998 3rd International Workshop on Statistical Metrology (Cat. No.98EX113)
Year: 1998 | Conference Paper |
Cited by: Papers (1)
The retrograde well implants for sub-0.18 /spl mu/m CMOS are done at a normal or near-normal incidence to minimize shadowing due to the thick photoresist edges. The endstation geometry in the high energy implanter results in an incident angle variation across the wafer, which causes strong spatial variations in the well profile and can negatively affect device performance. We show that the spatial...Show More
Toughening of thin films by high energy ion beams
Proceedings of 11th International Conference on Ion Implantation Technology
Year: 1996 | Conference Paper |
Refractory metal films tend to grow with a high degree of intrinsic tensile stress. As the film thickness increases, the integrated stress becomes high enough to cause loss of adhesion. In the present study, when chromium films on the order of 1 /spl mu/m were irradiated with Ni ions of energy 75 MeV, a reduction in strain as measured by X-ray diffraction was observed. Scratch Adhesion measurement...Show More
Photoresist integrity during high energy implant
Proceedings of 11th International Conference on Ion Implantation Technology
Year: 1996 | Conference Paper |
Cited by: Papers (5)
Photoresist integrity was evaluated on a commercial high-energy ion implanter operated up to the specified energy (1.7 MeV B or 3.0 MeV P) and power (1.0 MeV B at 1000 p/spl mu/A or 2.0 MeV P at 500 p/spl mu/A) limits. SEM Cross-sectional analysis of several photoresists showed that the proper cooling was maintained to avoid significant photoresist degradation. Photoresist shrinkage was observed, ...Show More
IEEE Account
Purchase Details
Profile Information
Need Help?
- US & Canada: +1 800 678 4333
- Worldwide: +1 732 981 0060
- Contact & Support
- About IEEE Xplore
- Contact Us
- Help
- Accessibility
- Terms of Use
- Nondiscrimination Policy
- Sitemap
- Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.