A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation

A two-stage continuous-time (CT) ΔΣ modulator with VCO quantizer (VCOQ) is presented. The presented modulator suppresses the VCOQ Voltage-to-Frequency nonlinearity through dual path cancellation to achieve high linearity. As an added advantage, this architecture exhibits strong immunity to the first stage quantization error leakage to the output due to gain mismatches between the two stages and temperature variations. Fabricated in a 65 nm CMOS technology, the prototype modulator operates at 1.5 GS/s and achieves 76.1 dB SNR, 73.5 dB SNDR, 88 dB SFDR and 76.1 dB dynamic range in 50 MHz bandwidth. This prototype demonstrates robust performance with less than 1.5 dB variation in SNDR for ±10% gain mismatch between the two stages. Also, the SNDR variation remains within 1 dB for a temperature variation of 0° C − 80° C. The modulator consumes 51.8 mW of power leading to a Walden FoM of 134 fJ/conv-step.

I. Introduction

In recent years, CMOS process scaling has led to the lowering of supply voltages and has inspired the development of time based quantization techniques as an alternative to voltage based quantization. Among several methods, VCO based quantizers (VCOQ) have become a popular choice for replacing conventional voltage based multibit quantizers. When used as a voltage-to-frequency converter, VCOQs have the desirable properties of inherent first order noise shaping and implicit dynamic element matching (DEM) [1]. Despite the above advantages, the highly nonlinear voltage-to-frequency (V-to-F) transfer characteristic of a VCOQ leads to performance degradation. When the VCOQ is used in a modulator, this nonlinearity degrades the distortion performance and limits the achievable SNDR [1]. In order to suppress the distortion, the order of the loop filter has to be increased more than that required for meeting the quantization noise specification, leading to a higher power consumption and stability issues. To overcome this non-linearity issue, the VCOQ has also been used as a voltage-to-phase converter [2], [3]. Although voltage-to-phase conversion solves the VCOQ non-linearity problem, it requires an explicit DEM which is one of the major power dissipating blocks at GHz range sampling frequencies. Also, introducing a DEM in the feedback path increases the excess-loop-delay (ELD) and sets a limit to the maximum achievable sampling frequency. Digital background calibration [5] has also been used to linearize the VCOQ. The architecture in [4] uses two stages to cancel the VCOQ nonlinearity and implements a second order NTF.