Abstract:
This paper reports Extremely-Thin-Body (ETB) InAs quantum-well (QW) MOSFETs with improved electrostatics down to Lg = 50 nm (S =103 mV/dec, DIBL = 73 mV/V). These excelle...Show MoreMetadata
Abstract:
This paper reports Extremely-Thin-Body (ETB) InAs quantum-well (QW) MOSFETs with improved electrostatics down to Lg = 50 nm (S =103 mV/dec, DIBL = 73 mV/V). These excellent metrics are achieved by using extremely thin body (1/3/1 nm InGaAs/InAs/InGaAs) quantum well structure with optimized layer design and a high mobility InAs channel. The ETB channel does not significantly degrade transport properties as evidenced by gm >1.5 mS/μm and vinj = 2.4 × 10 cm/s.
Published in: 2012 International Electron Devices Meeting
Date of Conference: 10-13 December 2012
Date Added to IEEE Xplore: 14 March 2013
ISBN Information:
ISSN Information:
Citations are not available for this document.
Contents Cites in Patents (2)Patent Links Provided by 1790 Analytics
1.
Leobandung, Effendi, "Method and structure for III-V FinFET"
Inventors:
Leobandung, Effendi
Abstract:
A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator substrate; forming a semiconductor extension on the fin, the semiconductor extension comprising a III-V compound semiconductor material that is different from a material forming the fin in the III-V compound semiconductor layer; forming a dummy gate structure and a spacer across and perpendicular to the fin; forming a source/drain layer on a top surface of the substrate adjacent to the dummy gate structure; planarizing the source/drain layer; removing the dummy gate structure to expose a portion of the semiconductor extension on the fin; removing the exposed portion of the semiconductor extension; etching the semiconductor extension to undercut the spacer; and forming a replacement gate structure in place of the removed dummy gate structure and removed exposed portion of the semiconductor extension.
Assignee:
INTERNATIONAL BUSINESS MACHINES CORP
Filing Date:
17 February 2016
Grant Date:
07 March 2017
Patent Classes:
Current International Class:
H01L0296600000, H01L0297800000, H01L0213360000, H01L0270880000, H01L0297750000, H01L0291000000, H01L0294000000, H01L0292050000, H01L0291500000
2.
Leobandung, Effendi, "Method and structure for III-V FinFET"
Inventors:
Leobandung, Effendi
Abstract:
A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator substrate; forming a semiconductor extension on the fin, the semiconductor extension comprising a III-V compound semiconductor material that is different from a material forming the fin in the III-V compound semiconductor layer; forming a dummy gate structure and a spacer across and perpendicular to the fin; forming a source/drain layer on a top surface of the substrate adjacent to the dummy gate structure; planarizing the source/drain layer; removing the dummy gate structure to expose a portion of the semiconductor extension on the fin; removing the exposed portion of the semiconductor extension; etching the semiconductor extension to undercut the spacer; and forming a replacement gate structure in place of the removed dummy gate structure and removed exposed portion of the semiconductor extension.
Assignee:
INTERNATIONAL BUSINESS MACHINES CORP
Filing Date:
20 October 2014
Grant Date:
15 November 2016
Patent Classes:
Current International Class:
H01L0213360000, H01L0270880000, H01L0296600000, H01L0297800000, H01L0297750000, H01L0291000000, H01L0294000000, H01L0292050000, H01L0291500000
