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Mi-Young Kim - IEEE Xplore Author Profile

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Author details

Mi-Young Kim

Publications

3

Citations

28

Publications by Year

20172019

Co-Authors:

Seung-Yeob BaekMichael ChoiIl-Hoon JangDong-Hwan JinDong-Shin Jo

Show All Co-Authors (17)

Mi-Young Kim

Affiliation

Department of Electrical Engineering

Korea Advanced Institute of Science and Technology

Daejeon, South Korea

Publication Topics

Current Source,
28-nm CMOS,
Access Time,
Analog Domain,
Analog-to-digital Converter,
Bit Error,
Bit Error Rate,
Circuit Implementation,
Conversion Rate,
Coupling Technique,
Current Reference,
Data Storage

Biography

Mi-Young Kim received the B.S. degree in electrical and computer engineering from the University of Seoul, Seoul, South Korea, in 2015, and the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2017.,Her research interests include synthesizable data converters.(Based on document published on 12 March 2019).

Publications

3

Citations

28

Publications by Year

20172019

Co-Authors:

Seung-Yeob Baek
Michael Choi
Il-Hoon Jang
Dong-Hwan Jin
Dong-Shin Jo

Show All Co-Authors (17)

Author's Published Works

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Showing 1-3 of 3 results

Conferences (2)

Journals (1)

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Single Year
Mi-Young Kim(3)
Seung-Tak Ryu(3)
Michael Choi(2)
Min-Jae Seo(2)
Seung-Yeob Baek(2)
KAIST, Daejeon, Korea(2)
SK Hynix, Icheon, South Korea(1)
2Samsung Electronics, Hwaseong, Korea(1)
Korea Advanced Institute of Science and Technology, Daejeon, Daejeon, KR(1)
Samsung Electronics, Hwaseong, Korea(1)
2017 Symposium on VLSI Circuits(2)
IEEE Journal of Solid-State Circuits(1)
IEEE(3)
Kyoto, Japan(2)
Current Source(2)
28-nm CMOS(1)
Access Time(1)
Analog Domain(1)
Analog-to-digital Converter(1)

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A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers

Dong-Hwan Jin;Ji-Wook Kwon;Min-Jae Seo;Mi-Young Kim;Min-Chul Shin;Seok-Joon Kang;Jung-Hyuk Yoon;Taek-Seung Kim;Seung-Tak Ryu

IEEE Journal of Solid-State Circuits

Year: 2019 | Volume: 54, Issue: 6 | Journal Article |

Cited by: Papers (4)

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This paper presents a reference-free readout method for the phase-change memory (PCM) that compensates for the temperature drift of the cell resistance. The proposed method reconfigures the sense amplifier (SA) array into flash analog-to-digital converters (ADCs) in order to extract the optimum decision threshold for the given temperature from the distribution of the data output therefrom. The res...Show More

A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers

Dong-Hwan Jin;Ji-Wook Kwon;Min-Jae Seo;Mi-Young Kim;Min-Chul Shin;Seok-Joon Kang;Jung-Hyuk Yoon;Taek-Seung Kim;Seung-Tak Ryu

IEEE Journal of Solid-State Circuits

Year: 2019 | Volume: 54, Issue: 6 | Journal Article |

A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS

Kyoung-Jun Moon;Hyun-Wook Kang;Dong-Shin Jo;Mi-Young Kim;Seung-Yeob Baek;Michael Choi;Hyung-Jong Ko;Seung-Tak Ryu

2017 Symposium on VLSI Circuits

Year: 2017 | Conference Paper |

Cited by: Papers (13) | Patents (1)

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A single-channel 10b pipelined SAR ADC with a gm-cell residue amplifier and a current-mode fine SAR ADC achieves a 500MS/s conversion rate in a 28nm CMOS process under a 1.0 V supply. With background offset and gain calibration, the prototype ADC achieves an SNDR of 56.6dB at Nyquist. With power consumption of 6mW, it obtains a FoM of 21.7fJ/conversion-step.Show More

A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS

Kyoung-Jun Moon;Hyun-Wook Kang;Dong-Shin Jo;Mi-Young Kim;Seung-Yeob Baek;Michael Choi;Hyung-Jong Ko;Seung-Tak Ryu

2017 Symposium on VLSI Circuits

Year: 2017 | Conference Paper |

A 4.2mW 10MHz BW 74.4dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC

Il-Hoon Jang;Min-Jae Seo;Mi-Young Kim;Jae-Keun Lee;Seung-Yeob Baek;Sun-Woo Kwon;Michael Choi;Hyung-Jong Ko;Seung-Tak Ryu

2017 Symposium on VLSI Circuits

Year: 2017 | Conference Paper |

Cited by: Papers (11)

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A compact and low-power digital-domain noise coupling technique is proposed for higher-order CT DSM implementation, exploiting the architectural advantage of a SAR ADC and a simple digital filter. With an 8b SAR ADC and a second-order digital noise coupling filter, a prototype fourth-order DSM achieves 74.4dB SNDR for 10MHz BW with an OSR of 16 in a 28nm CMOS, showing an FoMs_dr of 174.5dB.Show More

A 4.2mW 10MHz BW 74.4dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC

Il-Hoon Jang;Min-Jae Seo;Mi-Young Kim;Jae-Keun Lee;Seung-Yeob Baek;Sun-Woo Kwon;Michael Choi;Hyung-Jong Ko;Seung-Tak Ryu

2017 Symposium on VLSI Circuits

Year: 2017 | Conference Paper |

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