Test Whats new message.
Scheduled Maintenance on Monday 1/13/2025
Single article sales and account management will be unavailable from 5:00 AM - 7:00 PM ET (09:00 - 23:00 UTC). We apologize for the inconvenience.
International Conference on Parallel Architecture and Compilation Techniques (PACT)
2024 33rd International Conference on Parallel Architectures and Compilation Techniques (PACT)
13-16 Oct. 2024
Showing 1-25 of 28
Proceedings
The proceedings of this conference will be available for purchase through Curran Associates.
63594 - PACT, 2024 (PRT)
- Print on DemandPurchase at Partner
Sort By
PipeGen: Automated Transformation of a Single-Core Pipeline Into a Multicore Pipeline for a Given Memory Consistency Model
An Qi Zhang;Andrés Goens;Nicolai Oswald;Tobias Grosser;Daniel Sorin;Vijay Nagarajan
Publication Year: 2024,Page(s):1 - 13
Designing a pipeline for a multicore processor is difficult. One major challenge is designing it such that the pipeline correctly enforces the intended memory consistency model (MCM). We have developed the PipeGen design automation tool to allow architects to start with a single core pipeline that only enforces single-threaded correctness and automatically transform it to enforce a given MCM. Our ...Show More
Trimma: Trimming Metadata Storage and Latency for Hybrid Memory Systems
Publication Year: 2024,Page(s):108 - 120
Hybrid main memory systems combine both performance and capacity advantages from heterogeneous memory technologies. With larger capacities, higher associativities, and finer granularities, hybrid memory systems currently exhibit significant metadata storage and lookup overheads for flexibly remapping data blocks between the two memory tiers. To alleviate the inefficiencies of existing designs, we ...Show More
BoostCom: Towards Efficient Universal Fully Homomorphic Encryption by Boosting the Word-Wise Comparisons
Ardhi Wiratama Baskara Yudha;Jiaqi Xue;Qian Lou;Huiyang Zhou;Yan Solihin
Publication Year: 2024,Page(s):121 - 132
Fully Homomorphic Encryption (FHE) allows for the execution of computations on encrypted data without the need to decrypt it first, offering significant potential for privacy-preserving computational operations. Emerging arithmetic-based FHE schemes (ar-FHE), like BGV, demonstrate even better performance in word-wise comparison operations over non-arithmetic FHE (na-FHE) schemes, such as TFHE, esp...Show More
Leveraging Difference Recurrence Relations for High-Performance GPU Genome Alignment
Alberto Zeni;Seth Onken;Marco Domenico Santambrogio;Mehrzad Samadi
Publication Year: 2024,Page(s):133 - 143
Genome pairwise sequence alignment is one of the most computationally intensive workloads in many genomic pipelines, often accounting for over 90% of the runtime of critical bioinformatics applications. Recent advancements in sequencing technologies keep increasing the throughput of genomic sequencing data while decreasing the associated cost, emphasizing the need for fast and accurate software to...Show More
vSPACE: Supporting Parallel Network Packet Processing in Virtualized Environments through Dynamic Core Management
Gyeongseo Park;Minho Kim;Ki-Dong Kang;Yunhyeong Jeon;Sungju Kim;Hyosang Kim;Daehoon Kim
Publication Year: 2024,Page(s):14 - 25
Data centers face significant performance challenges with parallel processing for network I/O in virtualized environments, particularly for latency-critical (LC) workloads that must satisfy strict Service Level Objectives (SLOs). While previous studies have addressed performance challenges in network I/O virtualization, they overlook the impact of excessive parallelism on the performance of Virtua...Show More
Chimera: Leveraging Hybrid Offsets for Efficient Data Prefetching
Publication Year: 2024,Page(s):1 - 12
Data prefetching is an essential technique in contemporary high-performance processors for mitigating the effects of long-latency memory accesses. With the increasing demand for prefetcher to learn complex memory access patterns, many state-of-the-art prefetch-ers adopt methods such as using the program counter or access delta to separate memory access streams. This allows them to learn detailed m...Show More
Mirencoder: Multi-Modal IR-Based Pretrained Embeddings for Performance Optimizations
Publication Year: 2024,Page(s):156 - 167
One of the primary areas of interest in High Performance Computing is the improvement of performance of parallel workloads. Nowadays, compilable source code-based optimization tasks that employ deep learning often exploit LLVM Intermediate Representations (IRs) for extracting features from source code. Most such works target specific tasks, or are designed with a pre-defined set of heuristics. So ...Show More
NavCim: Comprehensive Design Space Exploration for Analog Computing-in-Memory Architectures
Publication Year: 2024,Page(s):168 - 182
Analog computing-in-memory (ACiM) technology has shown strong potential for neural network accelerators, addressing von-Neumann performance bottlenecks with in-memory data processing and computation. Understanding the ACiM design space, including its trade-offs and constraints, and systematically and effectively exploring it for optimal performance is essential to turn the promise into a viable pr...Show More
Mozart: Taming Taxes and Composing Accelerators with Shared-Memory
Vignesh Suresh;Bakshree Mishra;Ying Jing;Zeran Zhu;Naiyin Jin;Charles Block;Paolo Mantovani;Davide Giri;Joseph Zuckerman;Luca P. Carloni;Sarita V. Adve
Publication Year: 2024,Page(s):183 - 200
Resource-constrained system-on-chips (SoCs) are increasingly heterogeneous with specialized accelerators for various tasks. Acceleration taxes due to control and data movement, however, diminish end-to-end speedups from hardware acceleration. Meanwhile, emerging workloads are increasingly task-diverse with several, potentially shared, fine-grained acceleration candidates. This motivates a paradigm...Show More
PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory System
Steve Rhyner;Mohammad Sadrosadati;Harshita Gupta;Haocong Luo;Jiawei Jiang;Ce Zhang;Juan Gómez-Luna;Ataberk Olgun;Onur Mutlu
Publication Year: 2024,Page(s):201 - 218
Modern Machine Learning (ML) training on large-scale datasets is a very time-consuming workload. It relies on the optimization algorithm Stochastic Gradient Descent (SGD) due to its effectiveness, simplicity, and generalization performance (i.e., test performance on unseen data). Processor-centric architectures (e.g., CPUs, GPUs) commonly used for modern ML training workloads based on SGD are bott...Show More
Parallel Loop Locality Analysis for Symbolic Thread Counts
Fangzhou Liu;Yifan Zhu;Shaotong Sun;Chen Ding;Wesley Smith;Kaave Seyed Hosseini
Publication Year: 2024,Page(s):219 - 232
Data movement limits program performance. This bottleneck is more significant in multi-thread programs but more difficult to analyze, especially for multiple thread counts. For regular loop nests parallelized by OpenMP, this paper presents a new technique that predicts their miss ratio in the shared cache. It uses two statistical models, one for cache sharing and one for data sharing. Both models ...Show More
Improving Throughput-Oriented LLM Inference with CPU Computations
Publication Year: 2024,Page(s):233 - 245
Large language models (LLMs) have recently captured the attention of a broad audience. To a large part, their exceptional performance in text generation was made possible by an exponential growth of the model parameters. This growth, however, comes at the expense of significantly higher operational costs and a decreased processing speed. Recent research has focused on running LLMs on commodity har...Show More
ZeD: A Generalized Accelerator for Variably Sparse Matrix Computations in ML
Pranav Dangi;Zhenyu Bai;Rohan Juneja;Dhananjaya Wijerathne;Tulika Mitra
Publication Year: 2024,Page(s):246 - 257
Modern Machine Learning (ML) models employ sparsity to mitigate storage and computation costs; but it gives rise to irregular and unstructured sparse matrix operations that dominate the execution time and require specialized accelerators to meet the performance and energy targets. Contemporary sparse matrix accelerators, optimized for extreme sparsity, frequently fall short in addressing the varia...Show More
ACE: Efficient GPU Kernel Concurrency for Input-Dependent Irregular Computational Graphs
Sankeerth Durvasula;Adrian Zhao;Raymond Kiguru;Yushi Guan;Zhonghan Chen;Nandita Vijaykumar
Publication Year: 2024,Page(s):258 - 270
GPUs are widely used to accelerate many important classes of work-loads today. However, in this work, we observe that several important emerging classes of workloads, including simulation engines for deep reinforcement learning and dynamic neural networks, are unable to fully utilize the massive parallelism that GPUs offer. These applications tend to have kernels that are small in size, i.e., have...Show More
MORSE: Memory Overwrite Time Guided Soft — Writes to Improve ReRAM Energy and Endurance
Publication Year: 2024,Page(s):26 - 39
ReRAM is an attractive main memory technology due to its high density and low idle power. However, ReRAM exhibits costly writes, especially in terms of energy and endurance. Prior device studies show that retention can be traded off for write energy and endurance by employing soft write operations with lower currents. But given their reduced retention times, soft writes require refresh operations ...Show More
SZKP: A Scalable Accelerator Architecture for Zero-Knowledge Proofs
Publication Year: 2024,Page(s):271 - 283
Cited by: Papers (1)
Zero-Knowledge Proofs (ZKPs) are an emergent paradigm in verifiable computing. In the context of applications like cloud computing, ZKPs can be used by a client (called the verifier) to verify the service provider (called the prover) is in fact performing the correct computation based on a public input. A recently prominent variant of ZKPs is zkSNARKs, generating succinct proofs that can be rapidl...Show More
Boom: Use Your Desktop to Accurately Predict the Performance of Large Deep Neural Networks
Publication Year: 2024,Page(s):284 - 296
The intensive computational requirements of training deep neural networks (DNNs) have significantly driven the adoption of DNN accelerators like Graph Processing Units (GPU). However, selecting the most suitable GPU from all candidates with drastically different specifications and prices is still a challenging problem. While directly measuring the performance of DNN training tasks on every candida...Show More
Hash Tables are important data structures for a wide range of data intensive applications in various domains. They offer compact storage for sparse data, but their performance has difficulties to scale with the rapidly increasing volumes of data as they typically offer a single access port. Building a hash table with multiple parallel ports either has an excessive cost in memory resources, i.e., r...Show More
Recompiling QAOA Circuits on Various Rotational Directions
Enhyeok Jang;Dongho Ha;Seungwoo Choi;Youngmin Kim;Jaewon Kwon;Yongju Lee;Sungwoo Ahn;Hyungseok Kim;Won Woo Ro
Publication Year: 2024,Page(s):309 - 324
The quantum approximate optimization algorithm (QAOA) is introduced to efficiently solve combinatorial optimization problems. Despite the promise of QAOA, the cost of executing QAOA circuits at scale for quantum advantage may still be excessive for the near-future quantum device. We observe the increasing overhead of QAOA circuit execution in the native gate translation. To execute QAOA circuits o...Show More
Rethinking Page Table Structure for Fast Address Translation in GPUs: A Fixed-Size Hashed Page Table
Sungbin Jang;Junhyeok Park;Osang Kwon;Yongho Lee;Seokin Hong
Publication Year: 2024,Page(s):325 - 337
GPU memory virtualization has become essential for efficient programming, memory management, and address space sharing among computing devices in heterogeneous systems. Conventional GPU virtual memory systems use multi-level Radix Page Tables (RPTs) to store virtual-to-physical address mapping in device (GPU) memory. When a TLB miss occurs, a page table walker accesses each level of the page table...Show More
FriendlyFoe: Adversarial Machine Learning as a Practical Architectural Defense Against Side Channel Attacks
Hyoungwook Nam;Raghavendra Pradyumna Pothukuchi;Bo Li;Nam Sung Kim;Josep Torrellas
Publication Year: 2024,Page(s):338 - 350
Machine learning (ML)-based side channel attacks have become prominent threats to computer security. These attacks are often powerful, as ML models easily find patterns in signals. To address this problem, this paper proposes dynamically applying Adversarial Machine Learning (AML) to obfuscate side channels. The rationale is that it has been shown that intelligently injecting an adversarial pertur...Show More
Due to the sparse connectivity of superconducting quantum computers, qubit communication via SWAP gates accounts for the vast majority of overhead in quantum programs. We introduce a method for improving the speed and reliability of SWAPs at the level of the superconducting hardware's native gateset. Our method relies on four techniques: 1) SWAP Orientation, 2) Cross-Gate Pulse Cancellation, 3) Co...Show More
Optimizing Tensor Computation Graphs with Equality Saturation and Monte Carlo Tree Search
Publication Year: 2024,Page(s):40 - 52
The real-world effectiveness of deep neural networks often depends on their latency, thereby necessitating optimization techniques that can reduce a model's inference time while preserving its performance. One popular approach is to sequentially rewrite the input computation graph into an equivalent but faster one by replacing individual subgraphs. This approach gives rise to the so-called phase-o...Show More
Toast: A Heterogeneous Memory Management System
Maurice Bailleu;Dimitrios Stavrakakis;Rodrigo Rocha;Soham Chakraborty;Deepak Garg;Pramod Bhatotia
Publication Year: 2024,Page(s):53 - 65
Modern applications employ several heterogeneous memory types for improved performance, security, and reliability. To manage them, programmers must currently digress from the traditional load/store interface and rely on various custom libraries specific to each memory type, thus introducing programmability, performance, portability, and protection challenges. To overcome these challenges, we propo...Show More
Proceedings
The proceedings of this conference will be available for purchase through Curran Associates.
63594 - PACT, 2024 (PRT)
- Print on DemandPurchase at Partner
IEEE Account
Purchase Details
Profile Information
Need Help?
- US & Canada: +1 800 678 4333
- Worldwide: +1 732 981 0060
- Contact & Support
- About IEEE Xplore
- Contact Us
- Help
- Accessibility
- Terms of Use
- Nondiscrimination Policy
- Sitemap
- Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.