I. Introduction
Metal gate electrodes are projected to replace poly-Si gate for future CMOS devices in order to achieve equivalent oxide thickness (EOT) <1 nm according to the International Technology Roadmap for Semiconductors [1]. Metal gates have many advantages over poly-Si gates, such as no poly depletion effects, no boron penetration, and very low resistance and suppressed remote charge scattering [2]. In order to optimize threshold voltage Vt in high performance devices, tunable work function is needed for nMOS (in the range of 4.1–4.4 eV) and pMOS (in the range of 4.8–5.1 eV) devices. Several approaches have been investigated, including midgap metal gate [3], dual-metal CMOS integration [4][6] and fully silicided metal gate (FUSI) [7][13]. Detail Process Conditions for NiSi, CoSi<sub>2</sub> and Co<sub>x</sub>Ni<sub>1-x</sub>Si<sub>2</sub> FUSI Metal Gates Including Metal and Poly Thickness, Silicidation Temperature and Time, Dopant Dose and Energy, With or Without TiN Capping
TC. | T Ni | RTP | dopant | Gate dose | Energy | TiN | |
(A) | (A) | species | 1014cm−2 | KeV | |||
CoSi2 | 300 | 0 | 800° C 30s 60s,90s | B | 30 | 5 | w/ w/o |
Ni Si | 0 | 600 | 500°C 30s 60s,90s | As | 20 | 40 | |
CoxNi1-xSi2 | 200 | 100 | 800°c30s 60s,90s | undoped |