Loading web-font TeX/Math/Italic
The impact of TiN capping Layer on NiSi, CoSi/sub 2/, and Co/sub x/Ni/sub 1-x/Si/sub 2/ FUSI metal gate work function adjustment | IEEE Journals & Magazine | IEEE Xplore
Subscribe
ADVANCED SEARCH
Journals & Magazines >IEEE Transactions on Electron... >Volume: 52 Issue: 12

The impact of TiN capping Layer on NiSi, CoSi/sub 2/, and Co/sub x/Ni/sub 1-x/Si/sub 2/ FUSI metal gate work function adjustment

PDF
Jun Liu; Huang-Chun Wen; Jiong-Ping Lu; Dim-Lee Kwong
All Authors

Abstract:

The impact of TiN capping layer on dual work functions of Ni, Co, and Co-Ni fully silicided (FUSI) metal gates was investigated. It was found that the TiN capping layer s...Show More

Metadata

Abstract:

The impact of TiN capping layer on dual work functions of Ni, Co, and Co-Ni fully silicided (FUSI) metal gates was investigated. It was found that the TiN capping layer significantly altered the distribution of both n- and p-dopants during the FUSI process, which in turn changed the work functions of both As-doped and B-doped in the three FUSI metal gate systems. The work function tuning was found to have a linear relationship with the change of dopant level at the silicides/dielectric interface after adding TiN capping layer. The investigation of TiN capping layer on FUSI provided some insights on work function tuning mechanism in FUSI systems. This work also suggested a new methodology for optimizing the nMOS and pMOS work functions for CMOS device applications.
Published in: IEEE Transactions on Electron Devices ( Volume: 52, Issue: 12, December 2005)
Page(s): 2703 - 2709
Date of Publication: 31 December 2005

ISSN Information:

DOI: 10.1109/TED.2005.859700
Author image of Jun Liu
Microelectronics Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, Austin, TX, USA
Liu Jun received the B.S. degree in electrical engineering from Tsinghua University, Beijing, China, and the M.S. degree in electronics and computer engineering from the University of Texas at Austin 2002 and 2004, respectively. He is currently pursuing the Ph.D. degree at the Microelectronics Research Center, University of Texas at Austin.
His current research interests include work function control and reliability study ...Show More
Liu Jun received the B.S. degree in electrical engineering from Tsinghua University, Beijing, China, and the M.S. degree in electronics and computer engineering from the University of Texas at Austin 2002 and 2004, respectively. He is currently pursuing the Ph.D. degree at the Microelectronics Research Center, University of Texas at Austin.
His current research interests include work function control and reliability study ...View more
Author image of Huang-Chun Wen
Microelectronics Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, Austin, TX, USA
Huang-Chun Wen received the B.S. and M.S. degrees in electrical engineering from National ChiaoTung University, Hsinchu, Taiwan, R.O.C. She is currenlty pursuing the Ph.D. degree in electrical and computer engineering at The University of Texas at Austin.
She currently works on the electrical characterization and reliability measurements of metal gate and high-{\kappa} dielectric layers through internship in the Advanced...Show More
Huang-Chun Wen received the B.S. and M.S. degrees in electrical engineering from National ChiaoTung University, Hsinchu, Taiwan, R.O.C. She is currenlty pursuing the Ph.D. degree in electrical and computer engineering at The University of Texas at Austin.
She currently works on the electrical characterization and reliability measurements of metal gate and high-{\kappa} dielectric layers through internship in the Advanced...View more
Author image of Jiong-Ping Lu
Silicon Technology Development, Texas Instruments, Inc., Dallas, TX, USA
Jiong-Ping Lu (SM'01) was born in Fujian, China in 1962. He received the B.S degree from Peking University, Beijing, China, in 1982 and the Ph.D degree from Princeton University, Princeton, NJ, in 1989.
He was a Post-Doctoral Research Associate, Cornell University, Ithaca, NY, where he designed and set up a new laboratory for deposition and characterization of oxide, metal, and semiconductor thin films. He conducted post-d...Show More
Jiong-Ping Lu (SM'01) was born in Fujian, China in 1962. He received the B.S degree from Peking University, Beijing, China, in 1982 and the Ph.D degree from Princeton University, Princeton, NJ, in 1989.
He was a Post-Doctoral Research Associate, Cornell University, Ithaca, NY, where he designed and set up a new laboratory for deposition and characterization of oxide, metal, and semiconductor thin films. He conducted post-d...View more
Author image of Dim-Lee Kwong
Microelectronics Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, Austin, TX, USA
Dim-Lee Kwong (A'84–SM'90) received the B.S. degree in physics and the M.S. degree in nuclear engineering from the National Tsing Hua University, Taiwan, R.O.C., in 1977 and 1979, respectively, and the the Ph.D. degree in electrical engineering from Rice University, Houston, TX.
He was an Assistant Professor with the Electrical Engineering Department, University of Notre Dame, Notre Dame, IN, from 1982 to 1985. He was a Vi...Show More
Dim-Lee Kwong (A'84–SM'90) received the B.S. degree in physics and the M.S. degree in nuclear engineering from the National Tsing Hua University, Taiwan, R.O.C., in 1977 and 1979, respectively, and the the Ph.D. degree in electrical engineering from Rice University, Houston, TX.
He was an Assistant Professor with the Electrical Engineering Department, University of Notre Dame, Notre Dame, IN, from 1982 to 1985. He was a Vi...View more
Contents

I. Introduction

Metal gate electrodes are projected to replace poly-Si gate for future CMOS devices in order to achieve equivalent oxide thickness (EOT) <1 nm according to the International Technology Roadmap for Semiconductors [1]. Metal gates have many advantages over poly-Si gates, such as no poly depletion effects, no boron penetration, and very low resistance and suppressed remote charge scattering [2]. In order to optimize threshold voltage Vt in high performance devices, tunable work function is needed for nMOS (in the range of 4.1–4.4 eV) and pMOS (in the range of 4.8–5.1 eV) devices. Several approaches have been investigated, including midgap metal gate [3], dual-metal CMOS integration [4][6] and fully silicided metal gate (FUSI) [7][13]. Detail Process Conditions for NiSi, CoSi<sub>2</sub> and Co<sub>x</sub>Ni<sub>1-x</sub>Si<sub>2</sub> FUSI Metal Gates Including Metal and Poly Thickness, Silicidation Temperature and Time, Dopant Dose and Energy, With or Without TiN Capping

TC. T Ni RTP dopant Gate dose Energy TiN
(A) (A) species 1014cm−2 KeV
CoSi2 300 0 800° C 30s 60s,90s B 30 5 w/ w/o
Ni Si 0 600 500°C 30s 60s,90s As 20 40
CoxNi1-xSi2 200 100 800°c30s 60s,90s undoped

Author image of Jun Liu
Microelectronics Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, Austin, TX, USA
Liu Jun received the B.S. degree in electrical engineering from Tsinghua University, Beijing, China, and the M.S. degree in electronics and computer engineering from the University of Texas at Austin 2002 and 2004, respectively. He is currently pursuing the Ph.D. degree at the Microelectronics Research Center, University of Texas at Austin.
His current research interests include work function control and reliability study in novel FUSI metal gate for next-generation MOSFETs, novel SONOS memory using a high-{\kappa} layer as trapping layer, and rapid thermal processing for semiconductor materials and devices.
Liu Jun received the B.S. degree in electrical engineering from Tsinghua University, Beijing, China, and the M.S. degree in electronics and computer engineering from the University of Texas at Austin 2002 and 2004, respectively. He is currently pursuing the Ph.D. degree at the Microelectronics Research Center, University of Texas at Austin.
His current research interests include work function control and reliability study in novel FUSI metal gate for next-generation MOSFETs, novel SONOS memory using a high-{\kappa} layer as trapping layer, and rapid thermal processing for semiconductor materials and devices.View more
Author image of Huang-Chun Wen
Microelectronics Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, Austin, TX, USA
Huang-Chun Wen received the B.S. and M.S. degrees in electrical engineering from National ChiaoTung University, Hsinchu, Taiwan, R.O.C. She is currenlty pursuing the Ph.D. degree in electrical and computer engineering at The University of Texas at Austin.
She currently works on the electrical characterization and reliability measurements of metal gate and high-{\kappa} dielectric layers through internship in the Advanced Metal Electrode Group, SEMATECH, Austin.
Huang-Chun Wen received the B.S. and M.S. degrees in electrical engineering from National ChiaoTung University, Hsinchu, Taiwan, R.O.C. She is currenlty pursuing the Ph.D. degree in electrical and computer engineering at The University of Texas at Austin.
She currently works on the electrical characterization and reliability measurements of metal gate and high-{\kappa} dielectric layers through internship in the Advanced Metal Electrode Group, SEMATECH, Austin.View more
Author image of Jiong-Ping Lu
Silicon Technology Development, Texas Instruments, Inc., Dallas, TX, USA
Jiong-Ping Lu (SM'01) was born in Fujian, China in 1962. He received the B.S degree from Peking University, Beijing, China, in 1982 and the Ph.D degree from Princeton University, Princeton, NJ, in 1989.
He was a Post-Doctoral Research Associate, Cornell University, Ithaca, NY, where he designed and set up a new laboratory for deposition and characterization of oxide, metal, and semiconductor thin films. He conducted post-doctoral research on electronics packaging materials and MOCVD of III-V compound semiconductors at the Massachussets Institute of Technology, Cambridge. He is a Senior Member of Technical Staff at Texas Instruments, Inc., Dallas, TX. He has performed research and development in process technologies for CMOS devices of 180-, 130-, 90-, and 45-nm technology nodes. He has been active in a wide range of advanced metallization projects, including self-aligned silicides, metal gates, capacitor electrodes, diffusion barriers, and interconnects (W, Al and Cu). He was a key contributor and technical leader in the introduction of Cu and NiSi into TI fabs. He has been awarded 32 U.S. patents. He is an author or coauthor of more than 60 technical papers.
Dr. Lu was the recipient of the Harold W. Dodds Fellowship, an honors award from Princeton Graduate School in recognition of outstanding performance and professional promise.
Jiong-Ping Lu (SM'01) was born in Fujian, China in 1962. He received the B.S degree from Peking University, Beijing, China, in 1982 and the Ph.D degree from Princeton University, Princeton, NJ, in 1989.
He was a Post-Doctoral Research Associate, Cornell University, Ithaca, NY, where he designed and set up a new laboratory for deposition and characterization of oxide, metal, and semiconductor thin films. He conducted post-doctoral research on electronics packaging materials and MOCVD of III-V compound semiconductors at the Massachussets Institute of Technology, Cambridge. He is a Senior Member of Technical Staff at Texas Instruments, Inc., Dallas, TX. He has performed research and development in process technologies for CMOS devices of 180-, 130-, 90-, and 45-nm technology nodes. He has been active in a wide range of advanced metallization projects, including self-aligned silicides, metal gates, capacitor electrodes, diffusion barriers, and interconnects (W, Al and Cu). He was a key contributor and technical leader in the introduction of Cu and NiSi into TI fabs. He has been awarded 32 U.S. patents. He is an author or coauthor of more than 60 technical papers.
Dr. Lu was the recipient of the Harold W. Dodds Fellowship, an honors award from Princeton Graduate School in recognition of outstanding performance and professional promise.View more
Author image of Dim-Lee Kwong
Microelectronics Research Center, Department of Electrical and Computer Engineering, University of Texas, Austin, Austin, TX, USA
Dim-Lee Kwong (A'84–SM'90) received the B.S. degree in physics and the M.S. degree in nuclear engineering from the National Tsing Hua University, Taiwan, R.O.C., in 1977 and 1979, respectively, and the the Ph.D. degree in electrical engineering from Rice University, Houston, TX.
He was an Assistant Professor with the Electrical Engineering Department, University of Notre Dame, Notre Dame, IN, from 1982 to 1985. He was a Visiting Scientist with the IBM General Technology Division, Essex Junction, VT, during the summer of 1985, working on 4-Mb DRAM technology. He joined the Microelectronic Research Center and the Department of Electrical and Computer Engineering, The University of Texas, Austin, in 1985 as an Assistant Professor. He was promoted to Associate Professor in 1985 and to Full Professor in 1990. He is the author of more than 310 journal and 270 referred archival publications and has been awarded more than 22 U.S. patents. His current areas of research interests include rapid thermal CVD technology for the growth and deposition of semiconductor materials compatible with ULSI processes, advanced dielectrics for logic, analog, and memory devices, metal gate electrode, shallow junctions, and high dielectrics. Forty-three students received the Ph.D. degree under his supervision.
Dr. Kwong has received numerous awards, including the Best Dissertation Award in 1982, the IBM Faculty Development Award in 1984, and the Engineering Foundation Teaching Award from the University of Texas, Austin, in 1994. He also holds the Earl N. and Margaret Brasfield Endowed Fellowship.
Dim-Lee Kwong (A'84–SM'90) received the B.S. degree in physics and the M.S. degree in nuclear engineering from the National Tsing Hua University, Taiwan, R.O.C., in 1977 and 1979, respectively, and the the Ph.D. degree in electrical engineering from Rice University, Houston, TX.
He was an Assistant Professor with the Electrical Engineering Department, University of Notre Dame, Notre Dame, IN, from 1982 to 1985. He was a Visiting Scientist with the IBM General Technology Division, Essex Junction, VT, during the summer of 1985, working on 4-Mb DRAM technology. He joined the Microelectronic Research Center and the Department of Electrical and Computer Engineering, The University of Texas, Austin, in 1985 as an Assistant Professor. He was promoted to Associate Professor in 1985 and to Full Professor in 1990. He is the author of more than 310 journal and 270 referred archival publications and has been awarded more than 22 U.S. patents. His current areas of research interests include rapid thermal CVD technology for the growth and deposition of semiconductor materials compatible with ULSI processes, advanced dielectrics for logic, analog, and memory devices, metal gate electrode, shallow junctions, and high dielectrics. Forty-three students received the Ph.D. degree under his supervision.
Dr. Kwong has received numerous awards, including the Best Dissertation Award in 1982, the IBM Faculty Development Award in 1984, and the Engineering Foundation Teaching Award from the University of Texas, Austin, in 1994. He also holds the Earl N. and Margaret Brasfield Endowed Fellowship.View more
Contact IEEE to Subscribe
More Like This
Electrical characteristics of MILC poly-Si TFTs with long Ni-offset structure

IEEE Transactions on Electron Devices

Published: 2003

Self-aligned nickel, cobalt/tantalum nitride stacked-gate pMOSFETs fabricated with a low temperature process after metal electrode deposition

IEEE Transactions on Electron Devices

Published: 2003

Show More

References

References is not available for this document.

IEEE Account

Purchase Details

Profile Information

Need Help?

A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.