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The impact of TiN capping Layer on NiSi, CoSi/sub 2/, and Co/sub x/Ni/sub 1-x/Si/sub 2/ FUSI metal gate work function adjustment | IEEE Journals & Magazine | IEEE Xplore

The impact of TiN capping Layer on NiSi, CoSi/sub 2/, and Co/sub x/Ni/sub 1-x/Si/sub 2/ FUSI metal gate work function adjustment


Abstract:

The impact of TiN capping layer on dual work functions of Ni, Co, and Co-Ni fully silicided (FUSI) metal gates was investigated. It was found that the TiN capping layer s...Show More

Abstract:

The impact of TiN capping layer on dual work functions of Ni, Co, and Co-Ni fully silicided (FUSI) metal gates was investigated. It was found that the TiN capping layer significantly altered the distribution of both n- and p-dopants during the FUSI process, which in turn changed the work functions of both As-doped and B-doped in the three FUSI metal gate systems. The work function tuning was found to have a linear relationship with the change of dopant level at the silicides/dielectric interface after adding TiN capping layer. The investigation of TiN capping layer on FUSI provided some insights on work function tuning mechanism in FUSI systems. This work also suggested a new methodology for optimizing the nMOS and pMOS work functions for CMOS device applications.
Published in: IEEE Transactions on Electron Devices ( Volume: 52, Issue: 12, December 2005)
Page(s): 2703 - 2709
Date of Publication: 31 December 2005

ISSN Information:


I. Introduction

Metal gate electrodes are projected to replace poly-Si gate for future CMOS devices in order to achieve equivalent oxide thickness (EOT) <1 nm according to the International Technology Roadmap for Semiconductors [1]. Metal gates have many advantages over poly-Si gates, such as no poly depletion effects, no boron penetration, and very low resistance and suppressed remote charge scattering [2]. In order to optimize threshold voltage Vt in high performance devices, tunable work function is needed for nMOS (in the range of 4.1–4.4 eV) and pMOS (in the range of 4.8–5.1 eV) devices. Several approaches have been investigated, including midgap metal gate [3], dual-metal CMOS integration [4][6] and fully silicided metal gate (FUSI) [7][13]. Detail Process Conditions for NiSi, CoSi<sub>2</sub> and Co<sub>x</sub>Ni<sub>1-x</sub>Si<sub>2</sub> FUSI Metal Gates Including Metal and Poly Thickness, Silicidation Temperature and Time, Dopant Dose and Energy, With or Without TiN Capping

TC. T Ni RTP dopant Gate dose Energy TiN
(A) (A) species 1014cm−2 KeV
CoSi2 300 0 800° C 30s 60s,90s B 30 5 w/ w/o
Ni Si 0 600 500°C 30s 60s,90s As 20 40
CoxNi1-xSi2 200 100 800°c30s 60s,90s undoped

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