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Showing 1-15 of 15 resultsfor "Index Terms":digital-to-phase converter (DPC)
"Index Terms":digital-to-phase converter (DPC)
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A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL
Ahmed Elnaqib;Hayate Okuhara;Taekwang Jang;Davide Rossi;Luca Benini
Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs) for the Internet-of-Things (IoT). One recurrent issue with clock generators is multiple-phase generation, especially for low-power applications; several methods ...Show More
Dithering Concepts for Spur-Free Nonlinear DTC-Based Frequency Synthesizers
Christoph Preissl;Peter Preyler;Andreas Springer;Mario Huemer
Digital-to-time converters (DTCs) are a promising technology for radio frequency (RF) transceivers but are prone to spur generation. A common approach to change the spurious emissions to a spur-free shape is a method called dithering. The power added due to dithering is an important aspect of this approach and gives raise to investigations on additive dither as well as methods for subtractive dith...Show More
A Digital Pre-Distortion Technique for High-Linearity, Low-Power, Compact, Phase Interpolators
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2024 | Conference Paper |
Cited by: Papers (1)
The linearity of phase interpolators (PIs) is enhanced by pre-distorting the PI control weights, instead of increasing the number of clock phases. This approach shifts the design complexity from the analog to the digital domain, resulting in a PI with high linearity, low power consumption, low clock jitter, compact area. The optimized pre-distorted control weights effectively suppress the phase no...Show More
A 12-Bit 0.5–2.4-GHz 0.65°-Peak-INL Parasitic-Insensitive Digital-to-Phase Converter
Haoyun Jiang;Zhengkun Shen;Dong Wang;Xiucheng Hao;Zexue Liu;Yi Tan;Junhua Liu;Huailin Liao
A 12-bit 0.5–2.4-GHz parasitic-insensitive digital-to-phase converter (DPC) with high linearity is presented in this letter. A modified parasitic-insensitive charge-based (PICB) phase interpolator (PI) is proposed to avoid linearity degradation caused by parasitic effect. A novel PI cell with separated clock selecting logic is implemented to solve charge leakage and overcharging problem. The...Show More
A Wideband Digital Polar Transmitter with Integrated Capacitor-DAC-Based Constant-Envelope Digital-to-Phase Converter
Tong Li;Liang Xiong;Yun Yin;Yangzi Liu;Hao Min;Na Yan;Hongtao Xu
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Year: 2019 | Conference Paper |
Cited by: Papers (7)
This paper presents a wideband digital polar transmitter (DPTX) with integrated capacitor-DAC-based constant-envelope digital-to-phase converter (DPC). The switched-capacitor DAC topology is adopted to improve the linearity. The harmonic rejection and cell-reused techniques are employed to reject the 3rd/5th-order harmonics and reduce the power consumption, respectively. The measurement resu...Show More
A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS
Sebastian Sievert;Ofir Degani;Assaf Ben-Bassat;Rotem Banin;Ashoke Ravi;Wolfgang Thomann;Bernd-Ulrich Klepser;Zdravko Boos;Doris Schmitt-Landsiedel
This paper presents a 2 GHz digital-to-time converter (DTC) with 244 fs time resolution. The DTC consists of a multi-modulus divider (MMD) and a phase interpolator (PI) as coarse and fine tuning blocks, respectively. Control logic is implemented to prevent shoot-through current during the interpolation process in order to linearize the PI. The measured DTC's peak integral nonlinearity (INL) is 1.2...Show More
A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications
Meysam M. Khanghah;Khosrov D. Sadeghipour;Denis Kelly;Cleitus Antony;Peter Ossieur;Paul D. Townsend
This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the D...Show More
Analysis of Spectral Degradation and Error Compensation in 5G NR Digital Polar Transmitters
Christoph Preissl;Peter Preyler;Thomas Mayer;Andreas Springer;Mario Huemer
Cellular standards evolve to support increasingly higher bandwidths which results in strict in- and out-of-band requirements such as lower error vector magnitude (EVM) and/or adjacent channel leakage ratio (ACLR). Digital polar transmitters, which are showing the best performance in terms of power consumption, are challenged to fulfill these requirements. This work will show that even in case of i...Show More
An Accurate Fractional Period Delay Generation System
An all-digital technique is proposed for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A subsampling technique-based delay measurement unit (DMU) capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The proposed delay generation s...Show More
A 10 Bit Phase-Interpolator-Based Digital-to-Phase Converter for Accurate Time Synchronization in Ethernet Applications
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Year: 2020 | Conference Paper |
This work presents a 10 Bit digital-to-phase converter (DPC), for usage within an accurate time synchronization via Ethernet with a nominal frequency of 125 MHz. It is based on a 16-phase ring oscillator, stabilized by a phase-locked loop (PLL), followed by a 6 Bit phase-interpolator (PI). The DPC generates 1024 clock phases with a nominal resolution of 0.35°, covering a full 360° phas...Show More
A 0.1–1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection
This paper presents a digital-to-phase converter (DPC) with 8-bits of resolution and a wide frequency range for the input/output clocks. A harmonic rejection (HR) filter is introduced to improve linearity across a frequency range of 0.1-1.5 GHz. Instead of using time-domain averaging of phase interpolators (PI) in a conventional DPC, the frequency-domain filter directly cancels the 3rd...Show More
A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS
Chunxiao Hu;Yun Yin;Tong Li;Yangzi Liu;Liang Xiong;Hongtao Xu
This work presents a wideband digital polar transmitter (DPTX) with an integrated capacitor-digital-to-analog converter (C-DAC)-based digital-to-phase converter (DPC). A normalized CORDIC algorithm is introduced to convert the $I/Q$ baseband signals to a constant envelope to overcome the PM bandwidth expansion issue and avoid the amplitude modulation (AM)–phase modulation (PM) nonlinearity...Show More
Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <–103-dBc Spurious Tones Using Digital Spur Cancellation
In this article, we describe an advanced multi-output fractional frequency synthesizer (FFS) featuring an innovative digital spur cancellation technique. This technique not only effectively suppresses fractional- $N$ spurs but also eliminates externally coupled spurious tones. In addition, this article includes a comprehensive exploration of the proposed method, offering theoretical analysis and ...Show More
We compare the prior art in phase interpolators (PIs), classifying them as current-mode, voltage-mode, and integrating-mode PI. Next, we present an integrating-mode PI where the voltage slopes with high phase linearity are generated through the integration of phase-shifted weighted current sources. The constant and variable voltage slopes are generated by current sources/sinks created using stacke...Show More
A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter
Pavan Kumar Hanumolu;Volodymyr Kratyuk;Gu-Yeon Wei;Un-Ku Moon
A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent ...Show More
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