Loading web-font TeX/Main/Regular
A 17.7–19.2-GHz Receiver Front End With an Adaptive Analog Temperature- Compensation Scheme | IEEE Journals & Magazine | IEEE Xplore

A 17.7–19.2-GHz Receiver Front End With an Adaptive Analog Temperature- Compensation Scheme


Abstract:

This article presents an eight-element 17.7–19.2-GHz receiver front end with 1–2 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes a temperature-comp...Show More

Abstract:

This article presents an eight-element 17.7–19.2-GHz receiver front end with 1–2 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes a temperature-compensation variable-gain amplifier (TC-VGA) to minimize the temperature-induced gain variation. The concept of the proposed TC-VGA and the realization of corresponding adaptive analog control are introduced in detail. The front-end architecture and circuit-level design to enable a flat wideband gain response, precise phase and amplitude control, low power consumption, and adaptive analog temperature compensation are presented. Wafer probing is conducted to measure the performance of the receiver front end. The measured gain-temperature coefficient is ±0.005 dB/°C from −15°C to 85 °C at 17.7–19.2 GHz, while the counterpart without temperature compensation is −0.1 dB/°C. The chip demonstrates a 28-dB power gain, a 26% 3-dB fractional bandwidth, a 3.2–4.1-dB noise figure (NF), and a −27.4-dBm input 1-dB gain compression point (IP _{\mathrm {1\,dB}} ) for each element. In addition, each channel provides 7-bit phase-shifting resolution and 6-bit attenuation for a 15.75-dB gain range with a <1.5° root-mean-square (rms) phase error, and a < 0.22-dB rms amplitude error. The chip occupies 4.65\times2.77 mm2 area with pads, equivalent to 1.61 mm2 per element (for two beams), and consumes 37.2 mW per element per beam. To the best of our knowledge, the receiver front end demonstrates the minimum gain variation with temperature among silicon RF-beamforming front ends.
Published in: IEEE Transactions on Microwave Theory and Techniques ( Volume: 71, Issue: 3, March 2023)
Page(s): 1068 - 1082
Date of Publication: 31 October 2022

ISSN Information:

Funding Agency:

No metrics found for this document.

I. Introduction

Phased arrays have demonstrated great potential in 5G, satellite communication, radar, and sensor applications [1], [2], [3], [4], [5], [6], [7], [8], [9], [10]. Since silicon processes have high integration and low cost in mass production, they are widely adopted in phased-array design. The silicon-based phased array can integrate multiple channels in a single chip, reducing complex and lossy interconnections between front-end modules on a printed circuit board (PCB), thus benefitting the beamforming performance.

Usage
Select a Year
2025

View as

Total usage sinceNov 2022:1,553
010203040JanFebMarAprMayJunJulAugSepOctNovDec30290000000000
Year Total:59
Data is updated monthly. Usage includes PDF downloads and HTML views.
Contact IEEE to Subscribe

References

References is not available for this document.