1. Introduction
To tackle the emerging application needs of 8K ultra-high-definition (UHD) video broadcasting systems and related industry, the organizations for video coding standardization, such as Joint Video Experts Team (JVET) of ITU-T VCEG and ISO/IEC MPEG, and the Audio Video Coding Standard (AVS) working group of China, have put a lot of efforts into the development of new standards for efficient video compression, namely versatile video coding (VVC) [1] and the third generation of audio video coding standard (AVS3) [2], respectively. These burgeoning standards aim at supporting 4K/8K UHD video content, and expect to provide significant gains of coding efficiency. By better exploiting the potentials of parallelism and reusablity in modern video coding standards, the codec implementation efficiency can greatly benefit from hardware architecture customization compared with the software solutions based on general-purpose computing architecture. For instance, some recent works [3], [4] studied the hardware implementation of prediction and transform subsystems of the AVS3 coding standard, leaving the entropy encoder hardware an open problem to be investigated.