A Hardware Implementation of Entropy Encoder for 8K Video Coding | IEEE Conference Publication | IEEE Xplore

A Hardware Implementation of Entropy Encoder for 8K Video Coding


Abstract:

In this paper, we introduce an efficient hardware design for the third generation audio video coding standard (AVS3) based entropy coding, which satisfies the need of the...Show More

Abstract:

In this paper, we introduce an efficient hardware design for the third generation audio video coding standard (AVS3) based entropy coding, which satisfies the need of the emerging 8K video applications. The proposed hardware architecture is effectively established by partitioning functional modules for better dataflow organization. First, we customize the binarizer for massive parallelism. Second, by fully exploiting hardware sharing, a hardware/software co-design approach is initiated to optimize the pipelined throughput of the entropy coding engine. Third, we give an efficient buffer management method for sub-module coordination to ensure continuous bitstream generation. The proposed hardware design for entropy coding is the first work for the latest AVS3 video coding standard. The performance of the design is benchmarked based on the field-programmable gate array (FPGA) IP, which demonstrates the superior efficiency of hardware-accelerated entropy coding for streaming UHD media by achieving better design tradeoffs than the existing methods for previous standards.
Date of Conference: 18-22 July 2022
Date Added to IEEE Xplore: 26 August 2022
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Conference Location: Taipei, Taiwan

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1. Introduction

To tackle the emerging application needs of 8K ultra-high-definition (UHD) video broadcasting systems and related industry, the organizations for video coding standardization, such as Joint Video Experts Team (JVET) of ITU-T VCEG and ISO/IEC MPEG, and the Audio Video Coding Standard (AVS) working group of China, have put a lot of efforts into the development of new standards for efficient video compression, namely versatile video coding (VVC) [1] and the third generation of audio video coding standard (AVS3) [2], respectively. These burgeoning standards aim at supporting 4K/8K UHD video content, and expect to provide significant gains of coding efficiency. By better exploiting the potentials of parallelism and reusablity in modern video coding standards, the codec implementation efficiency can greatly benefit from hardware architecture customization compared with the software solutions based on general-purpose computing architecture. For instance, some recent works [3], [4] studied the hardware implementation of prediction and transform subsystems of the AVS3 coding standard, leaving the entropy encoder hardware an open problem to be investigated.

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