A Hardware Implementation of Entropy Encoder for 8K Video Coding

In this paper, we introduce an efficient hardware design for the third generation audio video coding standard (AVS3) based entropy coding, which satisfies the need of the emerging 8K video applications. The proposed hardware architecture is effectively established by partitioning functional modules for better dataflow organization. First, we customize the binarizer for massive parallelism. Second, by fully exploiting hardware sharing, a hardware/software co-design approach is initiated to optimize the pipelined throughput of the entropy coding engine. Third, we give an efficient buffer management method for sub-module coordination to ensure continuous bitstream generation. The proposed hardware design for entropy coding is the first work for the latest AVS3 video coding standard. The performance of the design is benchmarked based on the field-programmable gate array (FPGA) IP, which demonstrates the superior efficiency of hardware-accelerated entropy coding for streaming UHD media by achieving better design tradeoffs than the existing methods for previous standards.