Transient Response of ESD Protection Devices for a High-Speed I/O Interface

System-efficient electrostatic discharge (ESD) design (SEED) models of a diode and transient voltage suppressor (TVS) were developed to study their transient response in a high-speed input/output interface. Previously reported SEED models were improved to strengthen their convergence stability and facilitate accurate predictions over a wide range of conditions. These improvements were required to accurately capture the race conditions between the TVS and on-chip diode, where the diode's turn on may prevent turn on of the TVS. Simulations and measurements were performed to demonstrate the impact of the ESD pulse's rise time on race conditions. During a race, results showed the worst-case quasi-static diode current could be twice as high for long rise-time pulses than for short rise-times where the TVS does not turn on, and on-chip diode current may be larger at low test voltages than at high test voltages where the TVS does turn on. Adding a small passive impedance between the external TVS and the on-chip diode helps the TVS turn on and reduce the current through the on-chip diode by more than 50%. Similarly, lengthening the trace between the TVS and diode could reduce on-chip diode current by up to a factor of two.

I. Introduction

With the increasing speed of digital communication channels, the input/output (I/O) interface is at higher risk to electrostatic discharge (ESD) due to the thinner gate oxide of the I/O drivers and other FET characteristics. For a 35 nm complementary metal oxide semiconductor technology, the gate oxide film can be as thin as 1.2 nm, making it susceptible to damage from relatively small gate-to-source or gate-to-drain voltages. As logic gates shrink, there is increasing pressure to shrink the size of I/O cells, which means that the energy transferred during an ESD event can easily cause thermal damage to the on-die drivers and associated ESD protection [1].