A Novel Quaternary Multiplexer using CNTFET | IEEE Conference Publication | IEEE Xplore

A Novel Quaternary Multiplexer using CNTFET


Abstract:

Multiple-valued logic (MVL) is a propositional calculus in which there are more than two truth values. In binary system due to difficulty in interconnection problems MVL ...Show More

Abstract:

Multiple-valued logic (MVL) is a propositional calculus in which there are more than two truth values. In binary system due to difficulty in interconnection problems MVL preferred to solve and enhance in VLSI circuits. To work with MVL, Carbon Nano Tube Field-Effect Transistors (CNTFET) will be used. Quaternary multiplexer is one of the important circuit to be used in the design quaternary arithmetic and logic circuits. In this paper, the quaternary 4:1 Multiplexer designed using pass transistor logic to reduce the number of transistors. The proposed quaternary multiplexer design simulated using cadence Spectre with a CNTFET technology of 32-nm. The performance of these proposed design is tested for different parameters including power, delay and power delay product, with various supply voltages. The simulation results confirmed that the proposed quaternary multiplexer is better than existing one.
Date of Conference: 21-22 April 2022
Date Added to IEEE Xplore: 30 May 2022
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Conference Location: Coimbatore, India
Citations are not available for this document.

I. Introduction

Basically, one or more true values can be evaluated by multi-valued logic(MVL). MVL circuits have the capability to achieve high storage density compared to existing binary circuits. Using this beneficially we get more information with few number of connections in the circuits which mean reduce in power consumption and chip area [1].

Cites in Papers - |

Cites in Papers - IEEE (2)

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1.
Sarada Musala, P. Durga Vasavi, B. Spandana, Avireni Srinivasulu, Cristian Ravariu, "A Novel 2:1 Multiplexer Based Quaternary Full Adder", 2022 IEEE International Symposium on Smart Electronic Systems (iSES), pp.372-377, 2022.
2.
Yashika Gaidhani, Ashutosh Bagade, Monica Kalbande, Archana Kishorrao Vaidya, "Design of Universal Set of CMOS Gates using Multiple Valued Logic", 2022 International Conference on Emerging Trends in Engineering and Medical Sciences (ICETEMS), pp.368-372, 2022.

Cites in Papers - Other Publishers (1)

1.
G. V. S. Ajay, Sarada Musala, "Quaternary Multiplier with Modified Carry Using Carbon Nanotube FETs", Flexible Electronics for Electric Vehicles, vol.1065, pp.113, 2024.

References

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