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Design of Universal Set of CMOS Gates using Multiple Valued Logic | IEEE Conference Publication | IEEE Xplore

Design of Universal Set of CMOS Gates using Multiple Valued Logic


Abstract:

The design and implementation of digital circuits are performed in the binary logic switching algebra. The binary logic switching algebra is used to design and build digi...Show More

Abstract:

The design and implementation of digital circuits are performed in the binary logic switching algebra. The binary logic switching algebra is used to design and build digital circuits. We are developing a generic collection of gates for use in the synthesis and simplification of digital MV Logic circuits. Using digital circuits with multiple-valued logic, we can reduce the number of connections. MVL digital circuits can be designed by expanding the representation domain from the binary level (N=2) switching algebra to N > 2 levels. The implementation of an MVL digital circuit uses universal sets of MVL CMOS gates. The design and implementation of a universal set of CMOS gates are the topics of this work. In this paper we are dealing with the design and implementation of a universal set of CMOS gates, which includes extended AND operators: eANDl, eAND2,eAND3, Maximum operator and Successor operators for designing of any MVL digital circuits. Implemented circuits gives the proper functionality of the MVL combinational and sequential circuit design. In this MVL digital circuit uses voltage mode for operation having different range of voltages.
Date of Conference: 18-19 November 2022
Date Added to IEEE Xplore: 11 April 2023
ISBN Information:
Conference Location: Nagpur, India

I. Introduction

The two level logic (binary logic) switching algebra, where D is the domain of numerical representation, is typically used to implement digital circuits. The value of the digital representation domain must be increased to N levels in order to design Multiple Valued Logic circuits. D={0,1, 2 N- 1}. Many-valued or multi-valued logic are additional namesfor multiple valued logic (MVL). The universal gate design setis used to implement the sequential and combinational operators that operate in the B domain. As we embed several systems on a single integrated circuit (IC), or System on a Chip (SoC), the delay time as well as the complexity and length of the interconnections rise. To deal with the interconnection issues Multiple Valued logic is suitable optionas it reduces the number of interconnections [1].There are two technologies we can use for build MVL ICs, these are voltage mode and current mode. In the voltage mode, there are N number of logic levels. For defining logic levels different voltages as threshold are used in CMOS gates that is PMOS and NMOS transistors [3] and [4]. Supplementary Symmetrical Logic Circuit(SUSLOC) technology said that the MVL implementation needs less power consumption, improves the response time of MVL circuits compared with the binary logic and reduces the number of interconnection length [5]. Very few ICs are built in voltage mode proposals.

References

References is not available for this document.