I. Introduction
The two level logic (binary logic) switching algebra, where D is the domain of numerical representation, is typically used to implement digital circuits. The value of the digital representation domain must be increased to N levels in order to design Multiple Valued Logic circuits. D={0,1, 2 N- 1}. Many-valued or multi-valued logic are additional namesfor multiple valued logic (MVL). The universal gate design setis used to implement the sequential and combinational operators that operate in the B domain. As we embed several systems on a single integrated circuit (IC), or System on a Chip (SoC), the delay time as well as the complexity and length of the interconnections rise. To deal with the interconnection issues Multiple Valued logic is suitable optionas it reduces the number of interconnections [1].There are two technologies we can use for build MVL ICs, these are voltage mode and current mode. In the voltage mode, there are N number of logic levels. For defining logic levels different voltages as threshold are used in CMOS gates that is PMOS and NMOS transistors [3] and [4]. Supplementary Symmetrical Logic Circuit(SUSLOC) technology said that the MVL implementation needs less power consumption, improves the response time of MVL circuits compared with the binary logic and reduces the number of interconnection length [5]. Very few ICs are built in voltage mode proposals.