Impact of ex-situ and in-situ cleans on the performance of bipolar transistors with low thermal budget in-situ phosphorus-doped polysilicon emitter contacts

This paper investigates the effects of an in-situ hydrogen bake and an ex-situ hydrofluoric acid (HF) etch prior to polysilicon deposition on the electrical characteristics of bipolar transistors fabricated with low thermal budget in-situ phosphorus-doped polysilicon emitter contacts. Emitter contact deposition in a UHV-compatible low pressure chemical vapor deposition (LPCVD) cluster tool is also compared with deposition in a LPCVD furnace. Transmission electron microscopy (TEM) and secondary ion mass spectroscopy (SIMS) are used to characterize the emitter contact material and the interface structure and a comparison is made with Gummel plots and emitter resistances on bipolar transistors. The SIMS results show that an in-situ hydrogen bake in a cluster tool gives an extremely low oxygen dose at the interface of 6.3/spl times/10/sup 13/ cm/sup -2/, compared with 7.7/spl times/ 10/sup 14/ and 2.9/spl times/10/sup 15/ cm/sup -2/ for an ex-situ HF etch and deposition in a cluster tool or a LPCVD furnace, respectively. TEM shows that the in-situ hydrogen bake results in single-crystal silicon with a high density of defects, including dislocations and twins. The ex-situ HF etch gives polycrystalline silicon for deposition in both a cluster tool and a LPCVD furnace. The single-crystal silicon emitter contact has an extremely low emitter resistance of 21 /spl Omega/./spl mu/m/sup 2/ in spite of the high defect density and the light emitter anneal of 30 s at 900/spl deg/C. This compares with emitter resistances of 151 and 260 /spl Omega/./spl mu/ m/sup 2/ for the polycrystalline silicon contacts produced using an ex-situ HF etch and deposition in a cluster tool or a LPCVD furnace, respectively. These values of emitter resistance correlate well with the interface oxygen doses and the structure of the interfacial oxide layer. The high defect density in the single-crystal silicon is considered to be due to the high concentration of phosphorus (>5/spl times/10/sup 19/ cm/sup -3/) in the as-deposited layers.

I. Introduction

Polysilicon emitter contacts [1] have become a vital part of today's bipolar and BiCMOS technologies because they provide a means of realizing an exceptionally shallow emitter/base junction while maintaining a reasonable peripheral emitter/base capacitance. In polysilicon emitter contacts, an interfacial oxide layer is invariably present at the polysilicon/silicon interface, which has the advantage of increasing the current gain [2], [3] but the disadvantage of increasing the emitter resistance of the transistor [4]–[7]. A considerable amount of work has been published in the literature on the effects of the interfacial oxide on the base current [8]–[11] and emitter resistance [4] [5]– [7], [12], [13] of polysilicon emitter contacts. It has been found that the nature of the interfacial oxide is significantly influenced by a number of factors, including the type of ex-situ clean (typically an HF etch) used prior to polysilicon deposition [9], [14], the polysilicon deposition conditions [15], [16], and the subsequent annealing conditions [8]. A common requirement in all the work mentioned above is the need to achieve a well controlled interfacial oxide that gives low values of emitter resistance.