Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

Testing digital integrated circuits is generally done using Design-for-Testability (DfT) solutions. Such solutions, however, introduce non-negligible area and timing overheads that can be overcome by adopting functional solutions. In particular, functional test of integrated circuits plays a key role when guaranteeing the device's safety is required during the operative lifetime (in-field test), as required by standards like ISO26262. This can be achieved via the execution of a Self-Test Library (STL) by the device under test (DUT). Nevertheless, developing such test programs requires a significant manual effort, and can be non-trivial when dealing with complex modules. This paper moves the first step in defining a generic and systematic methodology to improve transition delay faults' observability of existing STLs. To do so, we analyze previously devised STLs in order to highlight specific points within test programs to be improved, leading to an increase in the final fault coverage.

I. Introduction

New advanced semiconductor technologies are increasingly adopted in emerging applications. Such technologies, however, are extremely complex and sophisticated, leading to more frequent physical defects and a reduced operative lifetime. Testing integrated circuits (ICs), hence, is of paramount importance. Some of these defects are tested by targeting delay faults, i.e., faults that affect the timing behavior of the device under test (DUT), such as transition delay faults (TDFs) or path delay faults (PDFs).