Riccardo Masante - IEEE Xplore Author Profile

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Author details

Riccardo Masante

Publications

3

Citations

11

Publications by Year

20212023

Co-Authors:

Lorena AnghelRiccardo CantoroFrancesco GarauPatrick GirardMichele Portolan

Show All Co-Authors (9)

Riccardo Masante

Affiliation

Department of DAUIN

Politecnico di Torino

Turin, Italy

Publication Topics

Clock Cycles,
Core Processes,
Electronic Design Automation,
Fault Simulation,
Testing Program,
Commercial Tools,
Deep Pipeline,
Defect Model,
Instruction Set Architecture,
Path Delay,
Test Pattern,
Area Overhead

Biography

Riccardo Masante received the M.S. degree in electronics engineering–embedded systems from the Politecnico di Torino, Turin, Italy, in 2020.,His thesis focused on finding new procedures to write ASM programs able to reach high-fault coverages for path delay faults.,Mr. Masante received the Graduation Award Techniques for Aging Detection of Processors in a Safety-Critical Environment.(Based on document published on 18 April 2023).

Publications

3

Citations

11

Publications by Year

20212023

Co-Authors:

Lorena Anghel
Riccardo Cantoro
Francesco Garau
Patrick Girard
Michele Portolan

Show All Co-Authors (9)

Author's Published Works

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Showing 1-3 of 3 results

Conferences (2)

Journals (1)

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Sandro Sartoni(3)
Riccardo Masante(3)
Riccardo Cantoro(3)
Matteo Sonza Reorda(3)
Michele Portolan(1)
Politecnico di Torino, Turin, Italy(1)
Department of DAUIN, Politecnico di Torino, Turin, Italy(1)
Department of Computer and Control Engineering, Politecnico di Torino, Turin, Italy(1)
Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Grenoble, France(1)
Univ. Grenoble Alpes, CEA, CNRS, Grenoble INP, IRIG-SPINTEC, Grenoble, France(1)
2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)(1)
2022 IEEE 40th VLSI Test Symposium (VTS)(1)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(1)
IEEE(3)
San Diego, CA, USA(1)
Torino, Italy(1)
Clock Cycles(3)
Core Processes(3)
Electronic Design Automation(3)
Fault Simulation(3)
Testing Program(3)

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Self-Test Library Generation for In-Field Test of Path Delay Faults

Lorena Anghel;Riccardo Cantoro;Riccardo Masante;Michele Portolan;Sandro Sartoni;Matteo Sonza Reorda

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2023 | Volume: 42, Issue: 11 | Journal Article |

Cited by: Papers (2)

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New semiconductor technologies for advanced applications are more prone to defects and imperfections related, among several different causes, to the manufacturing process, aging, and cross-talks. These phenomena negatively affect the circuit’s timing and can be effectively modeled by means of the path delay fault (PDF) model. While path delay testing is currently supported by commercial automatic ...Show More

Self-Test Library Generation for In-Field Test of Path Delay Faults

Lorena Anghel;Riccardo Cantoro;Riccardo Masante;Michele Portolan;Sandro Sartoni;Matteo Sonza Reorda

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2023 | Volume: 42, Issue: 11 | Journal Article |

Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries

Riccardo Cantoro;Francesco Garau;Riccardo Masante;Sandro Sartoni;Virendra Singh;Matteo Sonza Reorda

2022 IEEE 40th VLSI Test Symposium (VTS)

Year: 2022 | Conference Paper |

Cited by: Papers (1)

HTML

Functional test using a Software Test Library (STL) is becoming a standard solution for the in-field test of safety-critical systems, in compliance with functional safety standards, such as the ISO26262 for the automotive domain. However, developing high-quality test programs is considerably more challenging than generating scan test patterns through commercial tools, mainly due to the lack of mat...Show More

Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries

Riccardo Cantoro;Francesco Garau;Riccardo Masante;Sandro Sartoni;Virendra Singh;Matteo Sonza Reorda

2022 IEEE 40th VLSI Test Symposium (VTS)

Year: 2022 | Conference Paper |

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

Riccardo Cantoro;Patrick Girard;Riccardo Masante;Sandro Sartoni;Matteo Sonza Reorda;Arnaud Virazel

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)

Year: 2021 | Conference Paper |

Cited by: Papers (8)

HTML

Testing digital integrated circuits is generally done using Design-for-Testability (DfT) solutions. Such solutions, however, introduce non-negligible area and timing overheads that can be overcome by adopting functional solutions. In particular, functional test of integrated circuits plays a key role when guaranteeing the device's safety is required during the operative lifetime (in-field test), a...Show More

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement

Riccardo Cantoro;Patrick Girard;Riccardo Masante;Sandro Sartoni;Matteo Sonza Reorda;Arnaud Virazel

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)

Year: 2021 | Conference Paper |

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