Contents I. Introduction
The digital attenuators are widely used in radar, and other electronic equipment to achieve the magnitude of signal controlling. Especially in the modern phased array radar system, massive digital attenuators are employed to adjust signal magnitude of each path. Promoted by the demand, including phased array radar system and 5G mobile communication, high-performance digital attenuator design is always a hot topic in academy and industry [1–2]. The Circuit [2] employed switch path attenuator consists of two SPDTs and a -attenuator for the design of big attenuation bit to ensure low insertion loss, and in the band of 2-18-GHz the 6-bit digital attenuator realized less than 5.7-dB insertion loss with 31.5-dB dynamic attenuation range stepped by 0.5-dB in the band of 2-18-GHz. In [3], a 7-bit digital attenuator on SOI employing a number of switchable phase compensating blocks to compensate the phase shift is presented, and the attenuator has 7-bit attenuation with a 0.25-dB to 31.75-dB attenuation range in the band of 0.1 to 3.5-GHz while the maximum of insertion loss is 4.5-dB at 3.5-GHz. A 0.1-4.5GHz 5-bit digital attenuator is presented in [4] fabricated with SiGe BiCMOS process, and the insertion loss of the attenuator is less than 5.4-dB. In [5], a 25-30-GHz 6-bit digital attenuator with less than 5.7-dB insertion loss achieves better than 0.5-dB attenuation accuracy and less than 0.21-dB RMS attenuation error by applying an improved structure with a parallel capacitor, and employs a cascade structure of two switch transistors to enhance high isolation.
