A DC–Ka-Band 7-Bit Passive Attenuator With Capacitive-Compensation-Based Bandwidth Extension Technique in 55-nm CMOS

This article presents a 7-bit wideband passive attenuator with low insertion loss (IL) and high attenuation accuracy in 55-nm CMOS technology. The π-type and bridge-T-type attenuation units utilize an effective capacitive compensation technique, whose bandwidth extension mechanism is detailed in a single-unit pole-zero analysis. The matching-induced performance deterioration is investigated to minimize amplitude and phase errors at the chip level. The fabricated attenuator demonstrates a 32.4-dB attenuation range with a 0.255-dB resolution and a 3.5-8.4-dB IL from dc to 32 GHz. The measured root-mean-square (rms) amplitude and phase errors are below 0.32 dB and 5.33°, respectively. The attenuator occupies a 0.054-mm² core area and consumes negligible power.

I. Introduction

The arising low-Earth-orbit (LEO) satellite communication exploits silicon technologies to achieve low form factor and cost while suffering from temperature-related gain variations. Passive attenuators demonstrate low-temperature dependence and are suitable for digital temperature compensation. Compared with variable-gain amplifiers [1]–[3], passive attenuators provide wide tuning range, high resolution, low phase variation, high linearity, and wideband operation with negligible power consumption. Hence, beamformers often employ attenuators with a wide gain tuning range (i.e., 32 dB) to realize amplitude weighting with extra margin and a high resolution (i.e., ≤0.25 dB) to minimize beam jitter [4], [5]. In addition, analog beamforming prefers independent gain and phase control to reduce implementation complexity, imposing low insertion phase variation of the attenuator [6].