1 INTRODUCTION
The requirement for high computational power to support compute-intensive features in embedded system applications has drastically increased in the past few years [17]. To meet this requirement, the developers of these applications have started to employ multi-core architectures as opposed to the contemporary single-core architectures. However, the transition from single-core to multi-core is not trivial, especially in the case of real-time embedded systems, which have stringent timing requirements, e.g., timing constraints on the response times of tasks and data-propagation delays through chains of tasks [3], [5], [16], [21]. In the case of multi-core real-time embedded systems, the interference introduced due to the contention for shared resources such as the system bus and memories can lead to potentially unbounded delays [13], [31], [36]. Schedulability analysis techniques are used to ascertain if the specified timing constraints are met or not. Real-time scheduling and schedulability analysis for single-core real-time embedded systems are well developed and well adopted by the industry [10], [28]. Whereas, these techniques for multi-core real-time systems are still evolving [18].