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Work-in-Progress: Exploring Limited Preemption Approaches for the Phased Execution Model
2024 IEEE Real-Time Systems Symposium (RTSS)
Year: 2024 | Conference Paper |
Phased execution models separate computation from access to shared resources to make task execution predictable. These task models minimize interference between tasks, making them suitable for modern complex multi-core platforms. In the phased execution model, tasks perform computations only using the local memory to avoid accessing the shared memory during task execution. All instructions and dat...Show More
Towards Request Arbitration in Edge-Assisted Smart Intersections Under Timing Constraints
2024 IEEE 29th International Conference on Emerging Technologies and Factory Automation (ETFA)
Year: 2024 | Conference Paper |
Infrastructure-assisted autonomous driving has the potential to improve the decision-making process of autonomous driving. The car's perception can be augmented with information collected by infrastructure, such as smart intersections, that otherwise cannot be perceived by the car itself. This additional information enables more informed decisions, improving road safety. At the roadside unit, func...Show More
Multi-objective preference-free exact design space exploration of static DSP on multicore platforms
Rodolfo Jordão;Fahimeh Bahrami;Yu Yang;Matthias Becker;Ingo Sander;Kathrin Rosvall
2024 Forum on Specification & Design Languages (FDL)
Year: 2024 | Conference Paper |
A challenge in designing resource-constrained embedded systems for digital signal processing (DSP) is their complexity due to their vast design spaces, where only a fraction of implementations are feasible or optimal. A crucial tool to aid in this challenge is automated design space exploration (DSE). However, no exact, multi-objective, and preference-free DSE approach exists for DSP applications ...Show More
Meeting Job-Level Dependencies by Task Merging
2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)
Year: 2024 | Conference Paper |
Industrial applications are often time critical and subject to end-to-end latency constraints. Job-level dependencies can be leveraged to specify a partial ordering on tasks’ jobs already at early design phases, agnostic of the hardware platform or scheduling algorithm, and guarantee that end-to-end latency constraints of task chains are met as long as the job-level dependencies are respected. How...Show More
Design space exploration for safe and optimal mapping of avionics functionality on IMA platforms
Rodolfo Jordão;Matthias Becker;Ingo Sander;Ingemar Söderquist
2023 IEEE/AIAA 42nd Digital Avionics Systems Conference (DASC)
Year: 2023 | Conference Paper |
Future avionic systems will be increasingly automated. The size and complexity of the avionics functions in these systems will increase likewise. The degree of attainable automation directly depends on the avionics system's computing power and the efficiency of available tools that map the overall functionality onto the target heterogeneous platform architecture. In safety-critical scenarios, thes...Show More
On the QNX IPC: Assessing Predictability for Local and Distributed Real-Time Systems
2023 IEEE 29th Real-Time and Embedded Technology and Applications Symposium (RTAS)
Year: 2023 | Conference Paper |
With the advent of massively distributed applications such as those required by the IoT-to-Edge-to-Cloud compute continuum (i.e., automotive, smart agriculture, smart manufacturing, and more), real-time communication mechanisms allowing physically distributed nodes to seamlessly communicate as if they were running on the same host acquired noteworthy importance. To this end, the synchronous inter-...Show More
An Exact Schedulability Analysis for Global Fixed-Priority Scheduling of the AER Task Model
2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC)
Year: 2023 | Conference Paper |
Cited by: Papers (1)
Commercial off-the-shelf (COTS) multi-core platforms offer high performance and large availability of processing resources. In-creased contention when accessing shared resources is a result of the high parallelism and one of the main challenges when real-time applications are deployed to these platforms. As a result, sev-eral execution models have been proposed to avoid contention by separating ac...Show More
End-to-End Analysis of Event Chains under the QNX Adaptive Partitioning Scheduler
2022 IEEE 28th Real-Time and Embedded Technology and Applications Symposium (RTAS)
Year: 2022 | Conference Paper |
Cited by: Papers (7)
Modern autonomous cars run classic AUTOSAR applications alongside advanced driving assistance systems on a single-vehicle computer. Ensuring safety and predictability in such a complex system is challenging and requires temporal isolation between the various components. A promising solution is the POSIX-compliant QNX operating system: it meets the automotive standards for functional safety at the ...Show More
From the Synchronous Data Flow Model of Computation to an Automotive Component Model
Mehmet Onur Aybek;Rodolfo Jordao;John Lundbäck;Kurt-Lennart Lundbäck;Matthias Becker
2021 26th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA )
Year: 2021 | Conference Paper |
Cited by: Papers (2)
The size and complexity of automotive software systems are steadily increasing. Software functions are subject to different requirements and belong to different functional domains of the car. Meanwhile, streaming applications have become increasingly relevant in emerging application areas such as Advanced Driving Assistance Systems. Among models for streaming applications, the Synchronous Data Flo...Show More
Formulation of Design Space Exploration Problems by Composable Design Space Identification
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Year: 2021 | Conference Paper |
Cited by: Papers (4)
Design space exploration (DSE) is a key activity in embedded system design methodologies and can be supported by well-defined models of computation (MoCs) and predictable platform architectures. The original design model, covering the application models, platform models and design constraints needs to be converted into a form analyzable by computer-aided decision procedures such as mathematical pr...Show More
Constrained Data-Age with Job-Level Dependencies: How to Reconcile Tight Bounds and Overheads
Tobias Klaus;Matthias Becker;Wolfgang Schröder-Preikschat;Peter Ulbrich
2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS)
Year: 2021 | Conference Paper |
Cited by: Papers (18)
Many industrial real-time systems rely on the implicit register communication paradigm to minimize overheads and ease distributed development. Here, tasks follow a simple input-processing-output scheme, and data is passed without synchronization by the last-is-best semantics. In these systems, the age of data is the primary real-time objective, which is defined by data-flow chains that span from t...Show More
Optimizing Inter-Core Data-Propagation Delays in Industrial Embedded Systems under Partitioned Scheduling
Lamija Hasanagić;Tin Vidović;Saad Mubeen;Mahammad Ashjaei;Matthias Becker
2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)
Year: 2021 | Conference Paper |
This paper addresses the scheduling of industrial time-critical applications on multi-core embedded systems. A novel scheduling technique under partitioned scheduling is proposed that minimizes inter-core data-propagation delays between tasks that are activated with different periods. The proposed technique is based on the read-execute-write model for the execution of tasks to guarantee temporal i...Show More
From AMALTHEA to RCM and Back: a Practical Architectural Mapping Scheme
Alessio Bucaioni;Matthias Becker;John Lundbäck;Harald Mackamul
2020 46th Euromicro Conference on Software Engineering and Advanced Applications (SEAA)
Year: 2020 | Conference Paper |
Cited by: Papers (4)
This paper focuses on the mapping between two industrial architectural languages: AMALTHEA and Rubus Component Model. Both languages are heavily used within the automotive domain for the design and timing analysis of automotive software, respectively. The main contribution of this paper is a mapping scheme between the two architectural languages enabling i) the translation of an AMALTHEA architect...Show More
An Adaptive Resource Provisioning Scheme for Industrial SDN Networks
2019 IEEE 17th International Conference on Industrial Informatics (INDIN)
Year: 2019 | Conference Paper |
Cited by: Papers (4)
Many industrial domains face the challenge of ever growing networks, driven for example by Internet-of-Things and Industry 4.0. This typically comes together with increased network configuration and management efforts. In addition to the increasing network size, these domains typically are subject to adaptive load situations that pose an additional challenge on the network infrastructure.Software ...Show More
Static Allocation of Parallel Tasks to Improve Schedulability in CPU-GPU Heterogeneous Real-Time Systems
Nandinbaatar Tsog;Matthias Becker;Fredrik Bruhn;Moris Behnam;Mikael Sjödin
IECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society
Year: 2019 | Conference Paper |
Cited by: Papers (6)
Autonomous driving is one of the main challenges of modern cars. Computer visions and intelligent on-board decision making are crucial in autonomous driving and require heterogeneous processors with high computing capability under low power consumption constraints. The progress of parallel computing using heterogeneous processing units is further supported by software frameworks like OpenCL, OpenM...Show More
Towards QoS-Aware Service-Oriented Communication in E/E Automotive Architectures
IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society
Year: 2018 | Conference Paper |
Cited by: Papers (2)
With the raise of increasingly advanced driving assistance systems in modern cars, execution platforms that build on the principle of service-oriented architectures are being proposed. Alongside, service oriented communication is used to provide the required adaptive communication infrastructure on top of automotive Ethernet networks. A middleware is proposed that enables QoS aware service-oriente...Show More
Timing Analysis Driven Design-Space Exploration of Cause-Effect Chains in Automotive Systems
IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society
Year: 2018 | Conference Paper |
Cited by: Papers (1)
Model-based development and component-based software engineering have emerged as a promising approach to deal with enormous software complexity in automotive systems. This approach supports the development of software architectures by interconnecting (and reusing) software components (SWCs) at various abstraction levels. Automotive software architectures are often modeled with chains of SWCs, also...Show More
Architecting Safety Supervisors for High Levels of Automated Driving
Martin Törngren;Xinhai Zhang;Naveen Mohan;Matthias Becker;Lars Svensson;Xin Tao;De-Jiu Chen;Jonas Westman
2018 21st International Conference on Intelligent Transportation Systems (ITSC)
Year: 2018 | Conference Paper |
Cited by: Papers (15)
The complexity of automated driving poses challenges for providing safety assurance. Focusing on the architecting of an Autonomous Driving Intelligence (ADI), i.e. the computational intelligence, sensors and communication needed for high levels of automated driving, we investigate so called safety supervisors that complement the nominal functionality. We present a problem formulation and a functio...Show More
Scheduling multi-rate real-time applications on clustered many-core architectures with memory constraints
Matthias Becker;Saad Mubeen;Dakshina Dasari;Moris Behnam;Thomas Nolte
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Year: 2018 | Conference Paper |
Cited by: Papers (13)
Access to shared memory is one of the main challenges for many-core processors. One group of scheduling strategies for such platforms focuses on the division of tasks' access to shared memory and code execution. This allows to orchestrate the access to shared local and off-chip memory in a way such that access contention between different compute cores is avoided by design. In this work, an execut...Show More
A generic framework facilitating early analysis of data propagation delays in multi-rate systems (Invited paper)
Matthias Becker;Saad Mubeen;Dakshina Dasari;Moris Behnam;Thomas Nolte
2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
Year: 2017 | Conference Paper |
Cited by: Papers (7)
A majority of multi-rate real-time systems are constrained by a multitude of timing requirements, in addition to the traditional deadlines on well-studied response times. This means, the timing predictability of these systems not only depends on the schedulability of certain task sets but also on the timely propagation of data through the chains of tasks from sensors to actuators. In the automotiv...Show More
Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform
Matthias Becker;Borislav Nikolic;Dakshina Dasari;Benny Akesson;Vincent Nélis;Moris Behnam;Thomas Nolte
2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)
Year: 2017 | Conference Paper |
Cited by: Papers (11)
Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip (NoC), which is used for communication among the compute ...Show More
Buffer-Aware Analysis for Worst-Case Traversal Time of Real-Time Traffic over RRA-based NoCs
2017 25th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)
Year: 2017 | Conference Paper |
Cited by: Papers (3)
Network-on-Chip (NoC) is a communication subsystem which has been widely utilized in many-core processors and system-on-chips in general. In order to execute time-critical applications on a NoC-based platform, the timing behavior of the network needs to be predicted during system design. One of the most important timing requirements is regarding schedulability, which refers to determining if a rea...Show More
Using segmentation to improve schedulability of RRA-based NoCs with mixed traffic
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Year: 2017 | Conference Paper |
Network-on-Chip (NoC) is the interconnect of choice for many-core processors and system-on-chips in general. Most of the existing NoC designs focus on the performance with respect to average throughput, which makes them less applicable for real-time applications especially when applications have hard timing requirements on the worst-case scenarios. In this paper, we focus on a Round-Robin Arbitrat...Show More
A tighter recursive calculus to compute the worst case traversal time of real-time traffic over NoCs
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Year: 2017 | Conference Paper |
Cited by: Papers (4)
Network-on-Chip (NoC) is a communication subsystem which has been widely utilized in many-core processors and system-on-chips in general. In this paper, we focus on a Round-Robin Arbitration (RRA) based wormhole-switched NoC which is a common architecture used in most of the existing implementations. In order to execute real-time applications on such a NoC based platform, a number of given real-ti...Show More
Real-Time Capabilities of HSA Compliant COTS Platforms
Nandinbaatar Tsog;Matthias Becker;Marcus Larsson;Fredrik Bruhn;Moris Behnam;Mikael Sjödin
2016 IEEE Real-Time Systems Symposium (RTSS)
Year: 2016 | Conference Paper |
During recent years, the interest in using heterogeneous computing architecture in industrial applications has increased dramatically. These architectures provide the computational power that makes them attractive for many industrial applications. However, most of these existing heterogeneous architectures suffer from the following limitations: difficulties of heterogeneous parallel programming an...Show More
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