RiCoBiT - A topology for the future multi core processor: A concept analysis and review of literature

A Network On Chip (NOC) is a network-based technology that is used for intercommunication of data packets between the various modules present on a System On Chip (SOC). Originally, for this purpose, a simple Bus architecture was used which proved to be very inefficient in terms of latency and throughput. Other topologies like Mesh, 2D Torus, too proved inefficient when compared to the RiCoBiT architecture. This paper reviews the architecture of the novel RiCoBiT topology and assesses it in terms of maximum hop count, average hop count, interfaces, throughput and latency. These simulation results are compared with the previously present architectures like the 2D Mesh, Torus and are found to be more optimal in terms of scalability and efficiency of network communication.

I. INTRODUCTION

In everyday life, we are moving towards more utilization of electronic innovation and the concept of efficient communication between chip components comes into picture. This leads to appearance of framework on chip (SoC). SoC is commonly communicated as an IC which fundamentally joins all segment of a PC or hardware into a solitary chip. SoC was utilized to create portable phones, tablets and so on. SoC made these gadgets compact in size while increasing computing capacity and furthermore making it quicker than that of a PC. In defiance of circuit and process improvements, there was a huge utilization of power. Thus, diminishing devices to submicron dimensions, the voltage supply must be shortened to advert damaging electric fields. The increased requirement of heterogeneous core was becoming another issue because if one processor had high processing power then the other one had less power, for this reason the bandwidth, scalability and even the power efficiency was in high demand. Hindrance in system on chip directed network on chip to come into picture. Network on chip is used for sharing network, it has point to point link, computing module and a network switch. In NOC, communication is done by packet of bits. Routing of packets through several hop is done by switch. It also has efficient way of sharing wire and even it has parallelism. we can transfer data in the form of packets. It basically follows layered structure of protocol stack. Network on Chip consists of Routers Processing elements and a Network interface. It uses a Network which is like Wide area network (WAN) but it does not use Wide Area Network. This paper will be the discussion on a hybrid architecture that is Ring Connected Binary Tree, so that a better topology with reduced latency and increased bandwidth can be used in NOC. This paper also compares results of RiCoBiT architecture with those of mesh and 2D Torus in terms of max hop count, average hop count, wirelength, no of wire segments and gives an overall review of the optimal solution while providing future enhancements.