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Analysis of Network on Chip Topologies
2023 International Conference on Applied Intelligence and Sustainable Computing (ICAISC)
Year: 2023 | Conference Paper |
Cited by: Papers (3)
The incorporation of multi-core processors using current technologies is a challenging task as establishing effective communication among distant cores consumes significant time, ultimately diminishing the benefits of multi-core functionality. A new technology called Network on Chip (NoC) has been introduced to address this issue and is considered the future of the semiconductor industry. To devel...Show More
Compiling with MultiCores
2023 2nd International Conference for Innovation in Technology (INOCON)
Year: 2023 | Conference Paper |
Technology is evolving continuously at an exponential rate in terms of its performance. Traditional processors just have one core, however their computational capacity has been outgrown. Increasing the single core’s clock frequency is one technique to boost the system’s performance. A multitude of problems, including excessive power dissipation and CPU overheating, will arise when the frequency is...Show More
Field Programmable Gate Array(FPGA): An Innovation In Hardware Technology
2023 2nd International Conference for Innovation in Technology (INOCON)
Year: 2023 | Conference Paper |
FPGA is playing a significant role in the field of computer architecture and design. Other peer technologies of FPGA are embedded microprocessor and microcontroller. In this paper we are comparing the technologies which adapts to network-on-chip architecture. For embedded microprocessor and microcontroller, the hardware is already designed and we write the software instruction by exploiting the ha...Show More
RiCoBiT - A topology for the future multi core processor: A concept analysis and review of literature
Jude Abishek Satish;Hussam Taqhi;Harsh Mishra;P Chetana Reddy;V. Sanju
2020 International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE)
Year: 2020 | Conference Paper |
Cited by: Papers (2)
A Network On Chip (NOC) is a network-based technology that is used for intercommunication of data packets between the various modules present on a System On Chip (SOC). Originally, for this purpose, a simple Bus architecture was used which proved to be very inefficient in terms of latency and throughput. Other topologies like Mesh, 2D Torus, too proved inefficient when compared to the RiCoBiT arch...Show More
EAACK - Enhanced Adaptive Acknowledgment
V. Sanju;Gagana Venu;Reenu Sara Joseph;Mariya Stephen;Melvin Mathew
2018 Second International Conference on Computing Methodologies and Communication (ICCMC)
Year: 2018 | Conference Paper |
Wireless networks are currently dominating over wired networks in many applications.Mobility and scalability are some of the features that has led to make wireless networks more popular. Out of the many wireless network Mobile Ad-Hoc network (MANET) are the most popular. They have a highly dynamic and random topology. Essentially the ad hoc network is a collection of nodes communicating with each ...Show More
A fast and simple routing algorithm for butterfly architecture
2016 IEEE International Conference on Advances in Computer Applications (ICACA)
Year: 2016 | Conference Paper |
Cited by: Papers (1)
This paper presents the challenges we met during the development of simulators for NOC architectures. This paper focuses on the simulation of Buttery architecture. In earlier bus architectures when the size increases the communication between different nodes became a difficult task. The bus was a broadest module. It contains lots of lines. Its number is increasing. Some module is capturing this li...Show More
Network on chip simulator: Design, implementation and comparison of Mesh, Torus and RiCoBiT topologies
Nikhil Baby;Sangeetha Mathew;Sarah Abraham;Sampoorna Ravindranath;V. Sanju
2016 2nd International Conference on Next Generation Computing Technologies (NGCT)
Year: 2016 | Conference Paper |
Cited by: Papers (6)
The introduction of billions of transisters onto a single chip has resulted in the increase in complexity of the common System-on-Chip(SoC) architecture. The bus based architecture of SoC is limiting, mainly due to scalability issues. The solution for this communication problem is the use of embedded switching network, called Network On Chip(NoC). NoC has inherent redundancy which helps to tolerat...Show More
An exploration on lexical analysis
2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)
Year: 2016 | Conference Paper |
Cited by: Papers (6)
The word lexical in lexical analysis, its meaning is extracted from the word “lexeme”. Lexeme is an abstract unit of morphological analysis in linguistics. A lexical analyser is used in various applications like text editors, information retrieval system, pattern recognition programs and language compilers. But we limit our discussion in this paper to language compilers. Lexical analyser being the...Show More
Design of a generic network on chip frame work for store & forward routing for 2D mesh topology
2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems
Year: 2009 | Conference Paper |
The need of high performing, mega functionality solutions are becoming important day by day. The implementation of these mega functional modules which was done using common bus architecture, parallel bus architecture, pipelining are becoming ineffective and posing a bottleneck in terms of performance and throughput in this billion transistor era. To overcome these performance issues, a new paradig...Show More
The requirements of high performance mega functional solutions are becoming important day by day. With the advancement in semiconductor devices and fabrication technology, it is possible to pack more logic in smaller area of silicon. But the implementation of these mega functional modules using common bus architecture, parallel bus architecture, pipelining are becoming ineffective and posing a bot...Show More
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