Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of a circuit by as much as 50%.

I. Introduction

With the rapid growth of the portable electronics market in the last few years, the emphasis in VLSI design is shifting from high speed to low power. Portable applications like wireless communication and imaging systems (digital diaries, smart cards) demand high-speed computations, complex functionalities, and often real-time processing capabilities along with low power consumption.