Loading [MathJax]/extensions/MathZoom.js
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing | IEEE Conference Publication | IEEE Xplore

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing


Abstract:

The LEGaTO project leverages task-based programming models to provide a software ecosystem for Made in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dat...Show More

Abstract:

The LEGaTO project leverages task-based programming models to provide a software ecosystem for Made in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC, balanced with the security and resilience challenges. LEGaTO is an ongoing three-year EU H2020 project started in December 2017.
Date of Conference: 09-13 March 2020
Date Added to IEEE Xplore: 15 June 2020
ISBN Information:

ISSN Information:

Conference Location: Grenoble, France
References is not available for this document.

I. Introduction

In the last couple of decades, technological advances in the ICT sector have been the dominant factors in global economic growth, not to mention an increase in the quality of life for billions of people. At the heart of this advance lies Moore’s Law, which states that the number of transistors in an integrated chip will double every 18 to 24 months with each step in the silicon manufacturing technology node. However, due to the fundamental limitations of scaling at the atomic scale, coupled with heat density problems of packing an ever-increasing number of transistors in a unit area, Moore’s Law has slowed down in the last two years or so and will soon stop altogether [1]. The implication is that, in the future, the number of transistors that could be incorporated into a processor chip will not increase. This development threatens the future of the ICT sector as a whole. As a solution to this challenge, there has recently been a dramatic increase in efforts toward heterogeneous computing, including the integration of heterogeneous cores on die, utilizing general-purpose GPUs and combining CPUs, GPUs and FPGAs in integrated SoCs.

Select All
1.
Itrs international technology roadmap for semiconductors 2.0, 2015.
2.
Ward Van Heddeghem, Sofie Lambert, Bart Lannoo, Didier Colle, Mario Pickavet and Piet Demeester, "Trends in worldwide ict electricity consumption from 2007 to 2012", Computer Communications, vol. 50, pp. 64-76, 2014.
3.
René Griessl, Meysam Peykanu, Jens Hagemeyer, Mario Porrmann, Stefan Krupop, Micha vor dem Berge, et al., "A scalable server architecture for next-generation hetero-geneous compute clusters", 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing, pp. 146-153, 2014.
4.
Ariel Oleksiak, Michal Kierzynka, Wojciech Piatek, Giovanni Agosta, Alessandro Barenghi, Carlo Brandolese, William Fornaciari, Gerardo Pelosi, Mariano Cecowski, Robert Plestenjak et al., "M2dc–modular microserver datacentre with heterogeneous hardware", Microprocessors and Microsystems, vol. 52, pp. 117-130, 2017.
5.
Alejandro Duran, Eduard Ayguadé, Rosa M Badia, Jesús Labarta, Luis Martinell, Xavier Martorell, et al., "Ompss: a proposal for programming heterogeneous multi-core architectures", Parallel processing letters, vol. 21, no. 02, pp. 173-193, 2011.
6.
Miquel Pericas, "Poster: ξ-tao: A cache-centric execution model and runtime for deep parallel multicore topologies", Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, pp. 429-431, 2016.
7.
Behzad Salami, Osman S Unsal and Adrian Cristal Kestelman, "Comprehensive evaluation of supply voltage underscaling in fpga on-chip memories", 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 724-736, 2018.
8.
Behzad Salami, Osman S Unsal and Adrian Cristal Kestelman, "On the resilience of rtl nn accelerators: Fault characterization and mitigation", 2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pp. 322-329, 2018.
9.
L. Bautista-Gomez, S. Tsuboi, D. Komatitsch, F. Cappello, N. Maruyama and S. Matsuoka, "Fti: High performance fault tolerance interface for hybrid systems", SC ’11: Proceedings of 2011 International Conference for High Performance Computing Networking Storage and Analysis, 2011.
10.
Isabelly Rocha, Christian Göttel, Pascal Felber, Marcelo Pasin, Romain Rouvoy and Valerio Schiavoni, "Heats: Heterogeneity-and energy-aware task-based scheduling", 2019 27th Euromicro International Conference on Parallel Distributed and Network-Based Processing (PDP), pp. 400-405, 2019.
Contact IEEE to Subscribe

References

References is not available for this document.