Abstract:
Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the im...Show MoreMetadata
First Page of the Article
Abstract:
Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layers on the solder joint reliability of WLCSP on printed circuit boards (PCB) through creep responses such as deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped WLCSPs with pad-redistribution are considered in this study.
Published in: Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146)
Date of Conference: 03-03 October 2000
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-6482-1
Print ISSN: 1089-8190
First Page of the Article
Citations are not available for this document.
Cites in Patents (1)Patent Links Provided by 1790 Analytics
1.
Koning, Paul; Sterrett, Terry, "WAFER LEVEL UNDERFILL PROCESS MAKING USE OF SACRIFICIAL CONTACT PAD PROTECTIVE MATERIAL"
Inventors:
Koning, Paul; Sterrett, Terry
Abstract:
A method for connecting electronic components, such as, an integrated circuit die and a package substrate, is described. According to one aspect of the invention, a contact pad protective material is applied on one or more of the contact pads on an integrated circuit die. The underfill material is applied to the surface of the die not covered by the contact pad protective material and the underfill material is partially cured in a curing oven. The contact pad material is removed leaving openings over the respective surface of the contact pad. A one or more contacts on a package substrate is inserted into the openings, electronically connecting the contacts to the contact pads.
Assignee:
INTEL CORP
Filing Date:
07 June 2002
Grant Date:
13 June 2006
Patent Classes:
Current U.S. Class:
029852000, 029739000, 029740000, 029830000, 029840000, 029843000, 029846000, 174534000, 257E21503, 361760000, 439066000, 439068000, 439072000, 439074000, 439075000
Current International Class:
H01K0031000
