I. Introduction
The nonplanar FETs such as FinFETs have become the mainstream CMOS logic transistor in current-generation technology nodes due to their immunity to short channel effects [1]. SOI FinFETs are preferred than Bulk FinFET for our study due to its less sub-Fin leakage current, better electrostatic control over the channel and high-performance logic application in sub-10-nm technology node [2]. Further sub-10-nm node downscaling of FinFETs and other nonplanar FETs becomes a major technological challenge owing to systematic process variations and intrinsic device random fluctuations [3]. The major variability sources in FinFET characteristic variability are both systematic and random. The systematic sources are process-induced line edge roughness (LER) including Fin width roughness (FWR) and Fin height roughness (FHR) [4]–[6]. The random variability sources include intrinsic gate work function variability and random dopant fluctuations [3]. The characteristic variability challenges bring out the need for technological management of systematic variability and variability aware designs in technology modeling frameworks.