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Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10-nm Node SOI n-FinFET | IEEE Journals & Magazine | IEEE Xplore

Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10-nm Node SOI n-FinFET


Abstract:

We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-FET due to the impact of random fluctuation sources such as gate work ...Show More

Abstract:

We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-FET due to the impact of random fluctuation sources such as gate work function variability induced by metal gate granularity (MGG) and Fin line edge roughness (LER) using quantum corrected 3-D drift diffusion (DD) simulation framework. The statistical simulation predictions reveal that for ultra downscaled SOI FinFET, the MGG predominantly affects device threshold voltage. Similarly, the LER sources are found to strongly influence the variability of device short channel effect immunity and channel mobility of carriers. Both MGG and long correlation length LER are found to strongly influence the overlap and outer fringing parasitic capacitances variability, resulting in increased variability of device intrinsic speed. It is predicted that the presence of combined random fluctuation sources results in the increased variability of threshold mismatch index (AVT) for the sub-10-nm SOI FinFET technology.
Published in: IEEE Transactions on Electron Devices ( Volume: 66, Issue: 11, November 2019)
Page(s): 4646 - 4652
Date of Publication: 01 October 2019

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I. Introduction

The nonplanar FETs such as FinFETs have become the mainstream CMOS logic transistor in current-generation technology nodes due to their immunity to short channel effects [1]. SOI FinFETs are preferred than Bulk FinFET for our study due to its less sub-Fin leakage current, better electrostatic control over the channel and high-performance logic application in sub-10-nm technology node [2]. Further sub-10-nm node downscaling of FinFETs and other nonplanar FETs becomes a major technological challenge owing to systematic process variations and intrinsic device random fluctuations [3]. The major variability sources in FinFET characteristic variability are both systematic and random. The systematic sources are process-induced line edge roughness (LER) including Fin width roughness (FWR) and Fin height roughness (FHR) [4]–[6]. The random variability sources include intrinsic gate work function variability and random dopant fluctuations [3]. The characteristic variability challenges bring out the need for technological management of systematic variability and variability aware designs in technology modeling frameworks.

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