PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization

Recent advances in packaging technologies have improved multichip power module (MCPM) power density through innovative designs with layout size reduction, multi-layer stacking, and heterogeneous components integration. As these layout designs are getting denser, signal integrity issues due to mutual couplings demand more consideration. Hence, in order to handle these new layouts in the power module design automation tool-PowerSynth, a new electrical model has been developed based on the PEEC method. This method provides further insights into electrical reliability during optimization by evaluating current density and electric field inside each conductor. A coarse meshing process is applied to every generated layout to ensure accurate parasitic extraction while maintaining efficient computation time. Furthermore, a hierarchical approach has been applied to form connections between traces and components during placement to evaluate electrical parasitics without increasing the number of mesh points. Comparisons versus FEA simulation tools and experiments have shown promising initial extraction results using this model.

I. Introduction

Nowadays, the increased applications of wide bandgap (WBG) devices such as SiC and GaN in MCPMs have enabled high voltage, high current and fast switching power electronic circuits. At high switching frequencies, electrical parasitics are one of the most important metrics for MCPMs designs. This is because these unwanted elements can lead to voltage overshoot, current imbalance, and increased switching losses, which in turn reduce the reliability and achievable performance of the power electronic circuits they comprise. To overcome these issues, recent studies in MCPM design automation in [1] and [2] have applied fast extraction techniques to estimate parasitics values during layout optimization. In [2], the method of moments (MoM) calculations are first applied to extract current results. These results are then used in a boundary element method solver to extract loop inductance. More recently in PowerSynth [1], a response surface model is built prior to the layout optimization process for self-inductance and resistance of rectangular conductors to overcome the dimension ratio limitations of analytical equations. This method has been used along with a Laplacian matrix solver and has been shown to yield accurate loop parasitics approximation. Both of the methods above, however, do not consider the impact of mutual inductance coupling—which is of critical importance as MCPM package designs become ever denser. Hence, a new method needs to be developed for the PowerSynth layout optimization tool (Fig. 1).