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Quang Le - IEEE Xplore Author Profile

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Author details

Quang Le

Publications

15

Citations

167

Publications by Year

20162023

Co-Authors:

Imam Al RaziH. Alan MantoothAmol DeshpandeAsif Imran EmonTristan Evans

Show All Co-Authors (14)

Quang Le

Affiliation

Department of Electrical Engineering

University of Arkansas

Fayetteville, AR, USA

Publication Topics

Layout Optimization,
Application Programming Interface,
Loop Inductance,
Power Electronics,
Solution Space,
Finite Element Analysis,
Multichip Power Modules,
Packaging Technology,
Parasitic Inductance,
Design Constraints,
Design Flow,
Heat Transfer Coefficient

Biography

Quang Le (GS’16) received the B.S. (summa cum laude) degree in electrical engineering, in December 2015, from the University of Arkansas, Fayetteville, AR, USA, where he is currently working toward the Ph.D. degree in electrical engineering.,He is currently a Research Assistant with the University of Arkansas. His current research interests include design automation and optimization tools for power electronics modules.(Based on document published on 14 September 2018).

Publications

15

Citations

167

Publications by Year

20162023

Co-Authors:

Imam Al Razi
H. Alan Mantooth
Amol Deshpande
Asif Imran Emon
Tristan Evans

Show All Co-Authors (14)

Author's Published Works

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Showing 1-15 of 15 results

Conferences (11)

Journals (4)

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Single Year
Quang Le(15)
Yarui Peng(14)
H. Alan Mantooth(13)
Imam Al Razi(10)
Shilpi Mukherjee(6)
Department of Electrical Engineering, University of Arkansas, Fayetteville, AR, USA(4)
Electrical Engineering Department, University of Arkansas, Fayetteville, AR, US(4)
Computer Science and Computer Engineering Department, University of Arkansas, Fayetteville, AR, US(3)
Computer Science and Computer Engineering Department, University of Arkansas, Fayetteville, AR, USA(2)
Department of Computer Science and Computer engineering, University of Arkansas, Fayetteville, AR, USA(2)
IEEE Transactions on Power Electronics(3)
2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL)(1)
2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)(1)
2018 IEEE 19th Workshop on Control and Modeling for Power Electronics (COMPEL)(1)
2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)(1)
IEEE(15)
Media(1)
Bath, United Kingdom(2)
Albuquerque, NM, USA(1)
Atlanta, GA, USA(1)
Baltimore, MD, USA(1)
Detroit, MI, USA(1)
Layout Optimization(12)
Loop Inductance(10)
Finite Element Analysis(9)
Multichip Power Modules(8)
Parasitic Inductance(8)

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PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules

Imam Al Razi;Quang Le;Tristan M. Evans;H. Alan Mantooth;Yarui Peng

IEEE Transactions on Power Electronics

Year: 2023 | Volume: 38, Issue: 4 | Journal Article |

Cited by: Papers (16)

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Moving toward an electrified world requires ultrahigh-density power converters. With the adoption of wide-bandgap semiconductors (e.g., SiC and GaN), the next-generation power converters are on the horizon. However, the complexity of compact and high-speed converters is beyond the current industry-standard design flow based on manual and iterative steps. Therefore, research on design automation an...Show More

PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules

Imam Al Razi;Quang Le;Tristan M. Evans;H. Alan Mantooth;Yarui Peng

IEEE Transactions on Power Electronics

Year: 2023 | Volume: 38, Issue: 4 | Journal Article |

Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses

Quang Le;Imam Al Razi;Tristan M. Evans;Shilpi Mukherjee;Yarui Peng;H. Alan Mantooth

IEEE Journal of Emerging and Selected Topics in Power Electronics

Year: 2023 | Volume: 11, Issue: 6 | Journal Article |

Cited by: Papers (7)

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Recent studies in power electronic design automation have introduced various models for parasitic extraction of multichip power module layouts. However, none of these studies considers the eddy current effect in the direct-bonded-copper substrate, accounting for 40%–50% errors in the extraction result. This work introduces a methodology for eddy-current consideration through numerical simulation a...Show More

Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses

Quang Le;Imam Al Razi;Tristan M. Evans;Shilpi Mukherjee;Yarui Peng;H. Alan Mantooth

IEEE Journal of Emerging and Selected Topics in Power Electronics

Year: 2023 | Volume: 11, Issue: 6 | Journal Article |

Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization

Quang Le;Md Maksudul Hossain;Tristan Evans;Yarui Peng;H. Alan Mantooth

2022 IEEE Design Methodologies Conference (DMC)

Year: 2022 | Conference Paper |

Cited by: Papers (1)

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Along with the developments in power electronic packaging technology, many studies on design automation for MCPMs layout further push the design limits for their power density and compactness. Among these studies, PowerSynth has shown the complete design flow for MCPMs, which offers a multiobjective layout optimization algorithm and reduced-order models for electrical parasitic extraction and ther...Show More

Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization

Quang Le;Md Maksudul Hossain;Tristan Evans;Yarui Peng;H. Alan Mantooth

2022 IEEE Design Methodologies Conference (DMC)

Year: 2022 | Conference Paper |

Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation

Imam Al Razi;Quang Le;H. Alan Mantooth;Yarui Peng

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2021 | Conference Paper |

Cited by: Papers (4)

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Multi-chip power module (MCPM) layout design automation has become an emerging research field in the power electronics society. MCPM physical design is currently a trial-and-error procedure that heavily relies on the designers' experience to produce a reliable solution. To push the boundary of energy efficiency and power density, novel packaging technologies are emerging with increasing des...Show More

Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation

Imam Al Razi;Quang Le;H. Alan Mantooth;Yarui Peng

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2021 | Conference Paper |

Fast and Accurate Inductance Extraction for Power Module Layout Optimization Using Loop-Based Method

Quang Le;Imam Al Razi;Yarui Peng;H. Alan Mantooth

2021 IEEE Energy Conversion Congress and Exposition (ECCE)

Year: 2021 | Conference Paper |

Cited by: Papers (3)

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Electrical parasitics, especially parasitic inductance, play an essential role in enhancing power module design performance through reducing voltage overshoot and switching power losses. In this paper, a new electrical parasitic extraction model is developed, inspired by the loop-based extraction method from VLSI. This model shows only within 10% error compared to the FastHenry method while being ...Show More

Fast and Accurate Inductance Extraction for Power Module Layout Optimization Using Loop-Based Method

Quang Le;Imam Al Razi;Yarui Peng;H. Alan Mantooth

2021 IEEE Energy Conversion Congress and Exposition (ECCE)

Year: 2021 | Conference Paper |

PowerSynth Integrated CAD flow for High Density Power Modules

Quang Le;Imam Al Razi;Yarui Peng;H. Alan Mantooth

2021 IEEE Design Methodologies Conference (DMC)

Year: 2021 | Conference Paper |

Cited by: Papers (3)

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In the last few years, design automation for multi-chip power modules (MCPMs) has become a trending research topic in the power electronics community. Many different re-search efforts have demonstrated the advantages of bringing Computer-Aided Design (CAD) flow into MCPMs design and optimization. Among these works, PowerSynth has shown to have the most complete and mature CAD design flow for MCPMs...Show More

PowerSynth Integrated CAD flow for High Density Power Modules

Quang Le;Imam Al Razi;Yarui Peng;H. Alan Mantooth

2021 IEEE Design Methodologies Conference (DMC)

Year: 2021 | Conference Paper |

PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules

Imam Al Razi;Quang Le;Tristan M. Evans;Shilpi Mukherjee;H. Alan Mantooth;Yarui Peng

IEEE Transactions on Power Electronics

Year: 2021 | Volume: 36, Issue: 8 | Journal Article |

Cited by: Papers (28)

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As a critical energy-conversion system component, power semiconductor modules and their layout optimization has been identified as a crucial step in achieving the maximum performance and density for wide bandgap technologies (i.e., GaN and SiC). New packaging technologies are also introduced to produce reliable and efficient multichip power module (MCPM) designs to push the current limits. The com...Show More

PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules

Imam Al Razi;Quang Le;Tristan M. Evans;Shilpi Mukherjee;H. Alan Mantooth;Yarui Peng

IEEE Transactions on Power Electronics

Year: 2021 | Volume: 36, Issue: 8 | Journal Article |

Physical Design Automation for High-Density 3D Power Module Layout Synthesis and Optimization

Imam Al Razi;Quang Le;H. Alan Mantooth;Yarui Peng

2020 IEEE Energy Conversion Congress and Exposition (ECCE)

Year: 2020 | Conference Paper |

Cited by: Papers (6)

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With the on-going trend of electrification of transport, ultra-high-density power electronics with advanced 2.5D and 3D packaging are drawing attention. At present, the power module design is still a manual and time-consuming procedure. Floorplanning, placement, routing, and parasitic extraction need to be performed carefully to enhance performance without sacrificing reliability. Inspired by desi...Show More

Physical Design Automation for High-Density 3D Power Module Layout Synthesis and Optimization

Imam Al Razi;Quang Le;H. Alan Mantooth;Yarui Peng

2020 IEEE Energy Conversion Congress and Exposition (ECCE)

Year: 2020 | Conference Paper |

Hierarchical Layout Synthesis and Design Automation for 2.5D Heterogeneous Multi-Chip Power Modules

Imam Al Razi;Quang Le;H. Alan Mantooth;Yarui Peng

2019 IEEE Energy Conversion Congress and Exposition (ECCE)

Year: 2019 | Conference Paper |

Cited by: Papers (4)

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Multi-chip power module (MCPM) layout design automation has been identified as one of the primary research interests in the power electronics community with the advent of wide bandgap circuits. MCPM physical design requires a time-consuming iterative procedure that is so far explored manually based on the experience of the designers. Though the number of components and routing layers is limited in...Show More

Hierarchical Layout Synthesis and Design Automation for 2.5D Heterogeneous Multi-Chip Power Modules

Imam Al Razi;Quang Le;H. Alan Mantooth;Yarui Peng

2019 IEEE Energy Conversion Congress and Exposition (ECCE)

Year: 2019 | Conference Paper |

PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization

Quang Le;Tristan Evans;Yarui Peng;H. Alan Mantooth

2019 IEEE International Workshop on Integrated Power Packaging (IWIPP)

Year: 2019 | Conference Paper |

Cited by: Papers (11)

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Recent advances in packaging technologies have improved multichip power module (MCPM) power density through innovative designs with layout size reduction, multi-layer stacking, and heterogeneous components integration. As these layout designs are getting denser, signal integrity issues due to mutual couplings demand more consideration. Hence, in order to handle these new layouts in the power modul...Show More

PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization

Quang Le;Tristan Evans;Yarui Peng;H. Alan Mantooth

2019 IEEE International Workshop on Integrated Power Packaging (IWIPP)

Year: 2019 | Conference Paper |

PowerSynth: A Power Module Layout Generation Tool

Tristan M. Evans;Quang Le;Shilpi Mukherjee;Imam Al Razi;Tom Vrotsos;Yarui Peng;Homer Alan Mantooth

IEEE Transactions on Power Electronics

Year: 2019 | Volume: 34, Issue: 6 | Journal Article |

Cited by: Papers (50)

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PowerSynth is a multiobjective optimization tool for rapid design and verification of power semiconductor modules. By using reduced order models for the calculation of electrical parasitics of the layout and thermal coupling between devices, optimal trace layout and die placement can be simultaneously achieved orders of magnitude faster than conventional finite element analysis (FEA) techniques. A...Show More

PowerSynth: A Power Module Layout Generation Tool

Tristan M. Evans;Quang Le;Shilpi Mukherjee;Imam Al Razi;Tom Vrotsos;Yarui Peng;Homer Alan Mantooth

IEEE Transactions on Power Electronics

Year: 2019 | Volume: 34, Issue: 6 | Journal Article |

Constraint-Aware Algorithms for Heterogeneous Power Module Layout Synthesis and Reliability Optimization

Imam Al Razi;Quang Le;H. Alan Mantooth;Yarui Peng

2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)

Year: 2018 | Conference Paper |

Cited by: Papers (7)

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A constraint-aware layout engine is developed for PowerSynth to explore heterogeneous power module layout synthesis and optimization considering reliability. For this purpose, the corner stitching data structure with constraint graph evaluation is extended for power module layouts with generic, scalable, and efficient algorithms to place and route heterogeneous components including active devices,...Show More

Constraint-Aware Algorithms for Heterogeneous Power Module Layout Synthesis and Reliability Optimization

Imam Al Razi;Quang Le;H. Alan Mantooth;Yarui Peng

2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)

Year: 2018 | Conference Paper |

Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts

Shilpi Mukherjee;Tristan Evans;Balaji Narayanasamy;Quang Le;Asif Imran Emon;Amol Deshpande;Fang Luo;Yarui Peng;Steve Pytel;Tom Vrotsos;Alan Mantooth

2018 IEEE 19th Workshop on Control and Modeling for Power Electronics (COMPEL)

Year: 2018 | Conference Paper |

Cited by: Papers (14)

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As spacing between traces in power modules is reduced to meet increasing power density requirements, partial discharge (PD) starts becoming a threat that can cause insulation breakdown, if not checked. For high voltage applications, PD awareness is particularly important, and this paper describes how various trace shapes play a critical role in the electrical reliability of modules with regard to ...Show More

Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts

Shilpi Mukherjee;Tristan Evans;Balaji Narayanasamy;Quang Le;Asif Imran Emon;Amol Deshpande;Fang Luo;Yarui Peng;Steve Pytel;Tom Vrotsos;Alan Mantooth

2018 IEEE 19th Workshop on Control and Modeling for Power Electronics (COMPEL)

Year: 2018 | Conference Paper |

Response surface modeling for parasitic extraction for multi-objective optimization of multi-chip power modules (MCPMs)

Quang Le;Tristan Evans;Shilpi Mukherjee;Yarui Peng;Tom Vrotsos;H. Alan Mantooth

2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)

Year: 2017 | Conference Paper |

Cited by: Papers (11)

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In our tool, PowerSynth, fast calculation of electrical parasitics is of paramount concern when evaluating the layout of an MCPM during multi-objective optimization. To this end, this work extends the current capabilities of PowerSynth to quickly and more accurately extract lumped RLC parameters by utilizing a response surface model. An MCPM is represented as a series of layers forming a stack cor...Show More

Response surface modeling for parasitic extraction for multi-objective optimization of multi-chip power modules (MCPMs)

Quang Le;Tristan Evans;Shilpi Mukherjee;Yarui Peng;Tom Vrotsos;H. Alan Mantooth

2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)

Year: 2017 | Conference Paper |

Fast transient thermal and power dissipation modeling for multi-chip power modules: A preliminary assessment of different electro-thermal evaluation methods

Quang Le;Shilpi Mukherjee;Tom Vrotsos;H. Alan Mantooth

2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL)

Year: 2016 | Conference Paper |

Cited by: Papers (2)

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Increasing power density of high-switching frequency power modules presents a heat transfer challenge that left unaddressed can cause module failure. The first step in addressing this challenge is to estimate the maximum temperature that is observed in the module. PowerSynth, a multi-chip power module layout synthesis tool, utilizes a fast thermal model to quickly determine the steady-state maximu...Show More

Fast transient thermal and power dissipation modeling for multi-chip power modules: A preliminary assessment of different electro-thermal evaluation methods

Quang Le;Shilpi Mukherjee;Tom Vrotsos;H. Alan Mantooth

2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL)

Year: 2016 | Conference Paper |

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