A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator

A 10b flexible SAR ADC is presented incorporating a self-quenched dynamic bias comparator and a self-triggered asynchronous delay line. The ADC is fabricated in 65nm CMOS, occupies 0.04mm² and has an ENOB > 9bit and SFDR >66dB for sampling rates from 0.2 to 8MS/s at supply voltages respectively from 0.7V to 1.3V with a Walden FoM from 0.35 to 2.5fJ/conv-step. Keywords: SAR ADC, flexible, Walden Figure-of-Merit, SNDR, dynamic bias.

Introduction

SAR ADCs have high energy efficiency and are used in many IoT applications and low power radios. For these applications, sample rates vary from 0.1 to 10 MS/s [1]–. ADCs achieving lowest Walden Figure-of-Merit, FoM_W [1,2] reach that high energy efficiency only at a (few) fixed operating point(s). ADCs [3], [4] demonstrating flexibility over supply voltage, V_DD or sample rates do not achieve low FoM_W. This work introduces a low FoM_W SAR ADC that demonstrates flexibility in operation over V_DD and sample rates.