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A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier | IEEE Journals & Magazine | IEEE Xplore

A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier


Abstract:

Ternary content-addressable memory (TCAM) is limited by large cell area, high search power, significant active-mode leakage current, and a tradeoff between search speed a...Show More

Abstract:

Ternary content-addressable memory (TCAM) is limited by large cell area, high search power, significant active-mode leakage current, and a tradeoff between search speed and signal margin on the match-line (ML). In this paper, we developed a split-controlled single-load 14T (SCSL-14T) TCAM cell and a triple-margin voltage sense amplifier (TM-VSA) to achieve the following: 1) compact cell area; 2) lower search delay and search energy; 3) reduced current leakage in standby and active modes; and 4) tolerance for small sensing margin. A testchip with 320-Kb 14T-TCAM macro was fabricated using a 28-nm CMOS logic process and modified compact foundry six-transistor (6T) cell. The proposed macro achieved search delay of only 710 ps and 0.422 fJ/bit/search.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 54, Issue: 10, October 2019)
Page(s): 2743 - 2753
Date of Publication: 10 June 2019

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I. Introduction

Ternary content-addressable memory (TCAM) is commonly used in chips designed for networking and pattern recognition to compare input data against all patterns stored in activated parallel rows within a single access cycle. SRAM-based TCAMs have fast search times and unlimited endurance in terms of data updating; however, they impose a large cell area [1]–[5], [9]–[12]. Nonvolatile TCAMs (nvTCAM) use nonvolatile memory (NVM) devices, such as ReRAM [6]–[8], [37] and PCRAM [34], for pattern-storage and pattern-search comparisons. nvTCAM devices are relatively compact; however, they impose search delays longer than those of SRAM-based TCAM. Moreover, the constrained endurance of NVM devices limits the maximum number of data updates that can be performed during the lifetime of an nvTCAM macro. As shown in Fig. 1, typical 16 transistors (16T) TCAM cells include two six-transistor (6T)-SRAMs (M0–M5 and M6–M11) and four additional transistors (M12–M15). The two 6T SRAM cells store their data ( and ) in three storage states: pattern “1” (1, 0), “0” (0, 1), or “don’t-care” (X, (0, 0)). The 4T comparison circuits compare input data on the search-lines (SL and SLB) with pattern () stored in a TCAM cell and generate discharge current () on the match-line (ML) for cases of mismatch. For match operations, the ML is kept high. Table I lists the operating conditions of the three search operations: search-0, search-1, and search-X. Fig. 1(c) shows the layout of a 16T-TCAM. The right half includes two compact-rule SRAMs placed vertically. and are connected directly to M13 and M14 via a polysilicon gate. The SL and SLB are oriented vertically, whereas the ML is horizontal. The inclusion of a 4T comparison circuit breaks up the regularity of a 6T SRAM array, such that 4T circuits occupy a significant proportion in area of a 16T TCAM cell. Operating Conditions of the Three Search Operations of Conventional 16T-TCAM

Search DataSLSLBStored DataQQBModeML Voltage
001001Match1
110Mismatch0
X00Match1
110001Mismatch0
110Match1
X00Match1
X00001Match1
110Match1
X00Match1

(a) Structure of typical TCAM macro. (b) Schematic illustration. (c) Layout of conventional 16T TCAM cells.

References

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