Impact of conductance drift on multi-PCM synaptic architectures

In-memory computing with nanoscale memristive devices such as phase-change memory (PCM) has emerged as an alternative to conventional von Neumann systems to train deep neural networks (DNN) where a synaptic weight is represented by the device conductance. However, PCM devices exhibit temporal evolution of the conductance values referred to as the conductance drift, which poses challenges for maintaining synaptic weights reliably. Based on the mean behavior of 10,000 GST-based PCM devices, we observe that the drift coefficient is dependent on the conductance value. Moreover, we show that PCM drift is re-initialized and the drift history is erased after the application of even partial SET pulses. This is regardless of how much the device has drifted. With models capturing these features, we show that drift has a detrimental impact on training DNNs, but drift resilience can be significantly improved with a recently proposed multi-PCM synaptic architecture.

I. Introduction

The availability of big data has made it possible to achieve impressive human-like performance with deep neural networks (DNNs) [1]. However, training such networks on a von Neumann-based system where the computational unit and memory are physically separated is significantly slow and energy consuming due to the need to transfer the data between the two units. Recently, in-memory computing with memristive devices as synapses has shown promise for accelerating DNN training [2] –[4]. The synaptic weights can be represented by the device conductance. When arranged in a crossbar topology, all steps of DNN training - forward propagation, backpropagation, and weight update - can be performed in only O (1) time complexity in place, without the need to transfer any data [5].