An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor

An all-digital switched-capacitor (SC) based clock frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 processor. This fully-integrated unified clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% Vdd reduction (94% Vdd margin recovery) and a 3.2× increase in Fclk operating range.

Introduction

Conventional and regulation consists of two separate and independent control loops. As a result, the control loop is unaware of the impact of or temperature (T) changes on path timing margin. Thus, conventional designs require a significant margin to ensure correct operation at a target motivating adaptive techniques to reduce this margin [1], [2]. Recent work combines the and regulation into a single control loop using an LDO [3] and a buck converter [4]. By generating the core clock with a -powered tunable-replica oscillator (TRO), intrinsically adapts to and variations to compensate for critical-path-delay changes, and maintain a nearly constant timing margin independent of the regulation bandwidth. These systems continuously adjust to lock to a target reference frequency . In contrast to LDO or buck regulators, SC converters offer high efficiency and low-cost on-die integration. Traditional SC designs, however, suffer from poor load regulation and support a limited set of discrete voltages, which negatively affects dynamic voltage and frequency scaling (DVFS) opportunities. Configurable SC techniques [5], use of LDOs [6], or controlling SC output impedance in traditional two-loop systems overcome discrete SC ratio limitations, but these options limit the load-regulation range and are either complex, result in excessive headroom, or require large droop margin. This paper presents the first all-digital, SC-based UniCaP architecture (UniCaP-SC) to enable continuous scalability and margin reduction for high-efficiency and low-cost loT processors.