Parametric Study of p-n Junctions and Structures for CMOS-Integrated Single-Photon Avalanche Diodes

Single-photon avalanche diodes (SPADs) have emerged as the primary solid-state photodetectors for use in time-resolved imaging and very low light optical detection for their high sensitivity, fast impulse response, and CMOS process compatibility. For each application, diode structure and size must be optimized empirically, where device performance is difficult to predict theoretically. To assist in this iterative design process, this paper presents side-by-side characterization of multiple SPAD structures implemented using different p-n junctions in a single, deep sub-micron CMOS process. Detailed characterization of the sensors enables comparative analysis of important performance parameters, such as dark count rate and spectral response, across multiple p-n junction types, device structures, and SPAD size variants. A new approach for experimental analysis of after-pulsing is also presented. The characterized SPAD test array comprises multiple size and structural variants implemented in a general purpose 180nm CMOS process.

I. Introduction

Solid-State imagers enable state-of-the-art quantification of visible light in applications from biology, chemistry, medicine, and many other fields of science and engineering [1], [2]. In conventional silicon imagers, charged-coupled devices or CMOS photodetectors are widely used as pixel sensors, but these are limited by low-light performance and slow response [3], [4]. For fast or high-sensitivity applications, including medical imaging and light detection and ranging (LiDAR), low-light detection and fast impulse response are critical. These aims can be achieved using single-photon avalanche diode (SPAD) devices, which enable high sensitivity, fast response, and CMOS-integrability [5], [6]. SPAD detectors can also be used in conjunction with conventional photodetector-based imaging to extend optical dynamic range for visible light sensing [7]–[9].