Material Constraints and Scaling of 2-D Vertical Heterostructure Interlayer Tunnel Field-Effect Transistors

Aggressive scaling of logic devices is quickly approaching the physical limitations of conventional CMOS devices, resulting in the need for novel device architectures. One proposed device is the 2-D interlayer tunnel field-effect transistor (ITFET), which relies on tunneling within a vertical heterostructure of 2-D materials. Steep-slope operation of the ITFET relies on proper band alignment for tunneling between the conduction band of one 2-D electrode and the valence band of the other 2-D electrode. Because of the step-like nature of the density of states of transition metal dichalcogenides (TMDs), the subthreshold slope is infinite for ideal materials. Previous theoretical predictions suggested the possibility for steep-slope operation in TMD-based ITFETs, but did not consider the complete electronic and physical structure of the TMD electrodes. This paper explores the implications of the physical structure of materials, such as lattice constant, on ITFET performance. Further, several design parameters are explored within the MoS2-WSe2 system to develop general design rules for ITFETs based on 2-D materials. Benchmarking is performed of the MoS2-WSe2 ITFET to suggest the potential for both lower power and higher performance than conventional CMOS devices.

I. Introduction

Due to the continued scaling of logic devices over the past several decades, several physical limitations have emerged that require the development of novel device structures. In particular, the MOSFET architecture is limited to a subthreshold swing (SS) of 60 mV/decade by the slope of the Fermi function at room temperature. In order to continue scaling the bias voltage and the power consumption of these devices, a smaller SS is necessary, requiring alternative device architectures. Additionally, device scaling has been accompanied by increased OFF state currents and increased power density [1]. Each of these considerations complicates scaling of devices for future technology nodes.