A fast and simple routing algorithm for butterfly architecture

This paper presents the challenges we met during the development of simulators for NOC architectures. This paper focuses on the simulation of Buttery architecture. In earlier bus architectures when the size increases the communication between different nodes became a difficult task. The bus was a broadest module. It contains lots of lines. Its number is increasing. Some module is capturing this lines, transmitting electronic information and releasing into bus for somebody else to use. This bus based architectures of SoC could not solve many applications due to timing problem and so on. This is why we introduced the new paradigm of NoC. Basically this idea is to take this more less articulate and transform it into a very elegant kind of communication mean which we borrow from networking, i.e. routing short lines and we are putting routers in between. The future of VLSI is based on the NoC based architectures. To measure the performance simulation is inevitable. Thus we present this paper on the challenges we faced during the development of a simulator for buttery architecture.

I. Introduction

Earlier, semiconductor devices such as transistors, CMOS etc. were used in the design and implementation of digital systems. Later, semiconductor industry began to develop impressive developments in the large scale VLSI circuits. As a result a new embracing technology called System on Chip(SoC) was built, so that a single chip can accommodate the whole system. The drawback of this SoC technology was that, it was having a very large structure and integration was limited to few devices. These devices were connected using the traditional bus architecture for building the functional modules. In SoC, a large number of links are required to route packets through the network and it leads to network congestion. So a new paradigm called Network on Chip (NoC) was introduced. From the name suggests that NoC is organized for networks whereas SoC is organized for systems. The essential of this solution is that basically each module needs to connect to the network using some standard interface. This is because, today in industry we need to migrate from a design to another. This is actually one of the problem of the bus, if we want to increase the speed of bus and so on sometimes we have to modify the interface. We can actually place a constant interface so that we don't need to upgrade it every time the network becomes larger. Also we switch from words communication of bus to packet communication. We are doing real routing through micro routers. The traffic is being carried over these lines using statistical multiplexing. NoC can be often called as lifesavers, because NoC is connected with the SoC which significantly reduces the wiring connections required by the system to function. Other properties of NoC include the spatial reuse and design automation. We claim that this is really a paradigm shift in ways the chips are going to made. The paradigm shift means, like the hard-wired machines shifted to programmable chips, in logic synthesis the schematic capture shifted to HDLs and Cell Libraries. Here, the designers are affected with new design restrictions, new tools, new thinking etc. For every VLSI technicians working on new architectures of NoC this paper addresses the major challenges during the development of simulators. We also present the designs and implementation of nodes interfaces packets we used.