17.1 A digitally assisted CMOS WiFi 802.11ac/11ax front-end module achieving 12% PA efficiency at 20dBm output power with 160MHz 256-QAM OFDM signal

Front-end modules (FEM) typically employ expensive III-V or SiGe technologies to provide relatively higher PA output power and lower LNA noise figure (NF) for larger distance coverage compared to what can be achieved in a CMOS transceiver SoC [1]. The WiFi FEM is typically designed as a standalone entity using linear and inefficient PA topologies, such as Class-A/AB, resulting in an FEM not taking advantage of the full capability of the transceiver SoC. Furthermore, due to the stringent EVM requirement, almost 10dB back-off from P_sat is required, resulting in a poor PAE of <;7% at +20dBm P_out for the conventional Class-A/AB topologies regardless of device technology [1-3]. The CMOS FEM in Fig. 17.1.1 addresses the above issues and achieves performance comparable to that of GaAs/SiGe FEM but offers higher efficiency while using the full capability of the transceiver to enhance its performance. The proposed FEM integrates a PA, an LNA, a T/R switch, a transmit signal-strength indicator (TSSI) and an RF digital pre-distortion (DPD) calibration loopback path. It has two ICs integrated inside the same package. The PA, the LNA, and the DPD-loopback path are implemented on a 55nm bulk CMOS IC, while the T/R switch, PA output balun, and TSSI are integrated on a 0.18μm CMOS SOI IC.

Front-end modules (FEM) typically employ expensive III-V or SiGe technologies to provide relatively higher PA output power and lower LNA noise figure (NF) for larger distance coverage compared to what can be achieved in a CMOS transceiver SoC [1]. The WiFi FEM is typically designed as a standalone entity using linear and inefficient PA topologies, such as Class-A/AB, resulting in an FEM not taking advantage of the full capability of the transceiver SoC. Furthermore, due to the stringent EVM requirement, almost 10dB back-off from P_sat is required, resulting in a poor PAE of <7% at +20dBm Pout for the conventional Class-A/AB topologies regardless of device technology [1]–[3]. The CMOS FEM in Fig. 17.1.1 addresses the above issues and achieves performance comparable to that of GaAs/SiGe FEM but offers higher efficiency while using the full capability of the transceiver to enhance its performance. The proposed FEM integrates a PA, an LNA, a T/R switch, a transmit signal-strength indicator (TSSI) and an RF digital pre-distortion (DPD) calibration loopback path. It has two ICs integrated inside the same package. The PA, the LNA, and the DPD-Ioopback path are implemented on a 55nm bulk CMOS IC, while the T/R switch, PA output balun, and TSSI are integrated on a 0.18µm CMOS SOI IC.