Fatih Golcuk - IEEE Xplore Author Profile

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Front-end modules (FEM) typically employ expensive III-V or SiGe technologies to provide relatively higher PA output power and lower LNA noise figure (NF) for larger distance coverage compared to what can be achieved in a CMOS transceiver SoC [1]. The WiFi FEM is typically designed as a standalone entity using linear and inefficient PA topologies, such as Class-A/AB, resulting in an FEM not taking...Show More
This talk will present our latest work on silicon RFICs for phased-array applications with emphasis on very large chips with built-in-self-test capabilities for 5G systems. SiGe is shown to be ideal for mm-wave applications due to its high temperature performance (automotive radars, base-stations, defense systems, etc.) and lower power consumption. These chips drastically reduce the cost of microw...Show More
Presents a summary of the millimeter-wave wafer-scale phased array work at UCSD. This concept can drastically reduce the cost of millimeter-wave phased arrays by combining the RFIC blocks, antennas, power distribution and summing, digital control and up and down converters all on the same wafer (or large piece of silicon), and eliminates all RF transitions in and out of the chip, therefore resulti...Show More
This paper presents a 4×4 transmit/receive SiGe BiCMOS phased array at 90-100 GHz with vertical and horizontal polarization capabilities, and 3-bit amplitude and 4-bit phase control. The 4×4 phased array fits into a 1.6×1.5 mm2 grid, which is required at 94 GHz for wide scan-angle designs. This is accomplished using dual-nested 16:1 Wilkinson combiners/divider with > 40 dB isolation between the du...Show More
This paper presents a wideband 45 nm CMOS SOI quadrupler at 370 to > 430 GHz. The balanced multiplier results in a very low third harmonic component, and uses reflectors at the output port to reflect the fundamental and the second harmonic frequency into the quadrupler for improved efficiency. The measured output power is > 100 μW at 370-430 GHz with a peak value of 150-160 μW at 390-415 GHz and a...Show More
This paper presents a CMOS amplifier-multiplier-antenna array capable of generating an EIRP of 3-4 dBm at 420 GHz. The chip is built using a 45-nm CMOS SOI process, and efficient on-chip antennas are used to extract the power out of the chip. The design is based on a 90-110 GHz distribution network with splitters and amplifiers, and a balanced quadrupler capable of delivering up > 100 μW of power ...Show More
This paper presents the first built-in self-test system (BIST) for W-band transmit-receive phased-array modules. Low-loss high-isolation switches are attached to the RF input and output ports using λ/4 transmission-line sections, which result in a high shunt impedance when the BIST is disabled and minimal penalty in additional loss. A W-band in-phase/quadrature down-conversion mixer/receiver with ...Show More
This paper presents a 0.32 THz 4x4 imaging array based on an advanced SiGe technology. Each pixel is composed of a high efficiency on-chip antenna meeting all metal-density rules, which is coupled to a SiGe detector and a low noise CMOS operational amplifier. A quartz superstrate is used on top of the imaging chip to improve the radiation efficiency. The array results in an average NEP of 34 pW/Hz...Show More
This paper presents a 2×2 amplifier-multiplier array with on-chip antennas at 163-180 GHz in 45 nm CMOS SOI technology. The measured EIRP is > 2 dBm at 165-175 GHz with a peak value of 5 dBm at 170 GHz meeting the stringiest metal-density rules for antennas. The amplifiermultiplier architecture is scalable to N×M arrays for high EIRP and transmit power.Show More
This paper presents a 4 × 4 transmit/receive (T/R) SiGe BiCMOS phased-array chip at 90-100 GHz with vertical and horizontal polarization capabilities, 3-bit gain control (9 dB), and 4-bit phase control. The 4 × 4 phased array fits into a 1.6×1.5 mm2 grid, which is required at 94 GHz for wide scan-angle designs. The chip has simultaneous receive (Rx) beam capabilities (V and H) and this is accompli...Show More
Stacked field-effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors. The stacking of multiple FETs allows increasing the supply voltage, which, in turn, allows higher output power and a broader bandwidth output matching network. Different matching techniques for the intermediate nodes are anal...Show More
This paper presents the recent advances in sources and imaging arrays for >100 GHz applications. For sources, multiplier approach has recently demonstrated 1 mW of power at 200 GHz using 45 nm CMOS technology. For active imaging arrays, high-efficiency on-chip antennas coupled with low-noise CMOS SOI detectors are built at 300 GHz and 1 THz for low NEP systems.Show More