Abstract:
This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion,...Show MoreMetadata
Abstract:
This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-/spl Aring/ oxide MOS devices, transistors with channel lengths less than about 10 /spl mu/m will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance.
Published in: IEEE Transactions on Electron Devices ( Volume: 46, Issue: 8, August 1999)
DOI: 10.1109/16.777153
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA
Advanced Micro Devices, Inc., Sunnyvale, CA, USA
Advanced Micro Devices, Inc., Sunnyvale, CA, USA
HiPerMOS Device CoE, Motorola, Austin, TX, USA
Advanced Micro Devices, Inc., Sunnyvale, CA, USA
Advanced Micro Devices, Inc., Sunnyvale, CA, USA
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA
Advanced Micro Devices, Inc., Sunnyvale, CA, USA
Advanced Micro Devices, Inc., Sunnyvale, CA, USA
HiPerMOS Device CoE, Motorola, Austin, TX, USA
Advanced Micro Devices, Inc., Sunnyvale, CA, USA
Advanced Micro Devices, Inc., Sunnyvale, CA, USA
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA
