Abstract:
Using a 0.5 /spl mu/m baseline DRAM process, a single chip digital CMOS imaging system with SVGA pixel array, linear bank of 800 parallel 8 b ADCs, 3.2 kB DRAM buffer, di...Show MoreMetadata
Abstract:
Using a 0.5 /spl mu/m baseline DRAM process, a single chip digital CMOS imaging system with SVGA pixel array, linear bank of 800 parallel 8 b ADCs, 3.2 kB DRAM buffer, digital double sampling (DDS) circuitry and digital control is presented. A 3.3 V high-performance 4T nMOS, 8/spl times/8 /spl mu/m/sup 2/ pixel with on-chip RGB Bayer pattern color filters has measured green sensitivity >2 V/lux-s and dark current <25 pA/cm/sup 2/ at 25/spl deg/C. The chip is 7.6/spl times/8.6 mm/sup 2/ with 47% die efficiency, integrates over 2.2 M transistors, operates on a single 3.3 V power supply, and consumes <100 mW at 80 frame/s. The CMOS digital imaging system is packaged in a standard 20-pin cerDIP with quartz lid and implements programmable exposure time, RGB channel ADC gains and analog bias voltages and fixed pattern noise (FPN) cancellation and readout modes for image window panning and sizing.
Published in: 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)
Date of Conference: 17-17 February 1999
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-5126-6
Print ISSN: 0193-6530
