I. Introduction
Group III-V semiconductors are potential candidates for replacement of Si channel for complimentary metal-oxide-semiconductor (CMOS) logic applications because of. their high carrier mobility. However, reduction of electron trap density at high-k oxide/III-V interface is still the major challenge for III-V device technology in sub 10nm nodes [1], [2]. Conventional characterization methods primarily based on admittance measurements are unable to unambiguously determine interface trap density ( [3]–[8]; in particular, they cannot distinguish between free carriers and trapped carriers with fast response. In addition, III-V materials have low density of conduction band states and relatively high density of border traps [9], [10] that can have very fast (up to GHz) response [11] contributing to C-V measurements even under strong inversion conditions in contrast with Si MOS structures. Conventional methods employing a combination of C-V and I-V characteristics to estimate the effective mobility in the channel [5], [6], [12]–[15] result in over-estimation of channel charge thereby leading to under-estimation of carrier mobility. In this work, we use a gated Hall method to find the mobility and in an In0.53Ga0.47As inversion channel. Gated Hall method [12], [16]–[19] extracts without assumption of the trapping rates and the mobility is obtained from the Hall/conductivity measurements. Previously, we used gated Hall method to extract and mobility in buried InGaAs channels [17]–[19].