A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

This paper proposes a fully-digital BIST architecture for the dynamic test of ΣΔ ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the ΣΔ modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a test with a higher dynamic range that covers the full scale of the ADC. The output response is analyzed on-chip using a simplified version of the sine-wave fitting algorithm to compute the SNDR. A standard SPI bus provides digital external access to the embedded test instruments. The proposed BIST wrapper has been integrated into a 40 nm CMOS 18-bit stereo audio ΣΔ ADC IP core provided by ST Microelectronics. It incurs an overall area overhead of 7.1% and the total test time is 28 ms per channel. Experimental results on fabricated chips demonstrate an excellent correlation between the BIST and the standard functional specification test.

I. Introduction

Current market trends in the IC industry towards the design of highly integrated mixed-signal Systems-on-Chip (SoCs) and heterogeneous Systems-in-Package (SiPs) are supported by the reuse of parametrized Intellectual Property cores (IPs)—either in-house developed or provided by different IP vendors— that implement different analog, mixed-signal, and digital functions within the system. Testing the digital IP cores in these systems is a relatively straightforward task. A wide variety of broadly proven Design-for-Test (DfT) strategies for accessing these cores and evaluating their correct functionality are routinely embedded in every digital IP. These DfT strategies are built on the concepts of standardized scan chain buses and structural tests. On the other hand, testing mixed-signal IP cores in these systems still relies on functional specification testing. Functional specification testing uses specialized automated test equipment (ATE) for applying appropriate test stimuli, retrieving the output responses, and processing the test results. However, in a complex SoC/SiP—where the external access to the internal IPs is difficult, or directly impossible—these operations may turn challenging to perform at a reasonable cost [1]. Indeed, it has been estimated that the cost of testing mixed-signal IP cores has already become the dominant contribution to the overall manufacturing cost [2].