3.8-MV/cm Breakdown Strength of MOVPE-Grown Sn-Doped $\beta $ -Ga2O3 MOSFETs

A Sn-doped (100) $\beta $ -Ga₂O₃ epitaxial layer was grown via metal–organic vapor phase epitaxy onto a single-crystal, Mg-doped semi-insulating (100) $\beta $ -Ga₂O₃ substrate. Ga₂O₃-based metal–oxide–semiconductor field-effect transistors with a 2- $\mu \text{m}$ gate length ( $L_{G})$ , 3.4- $\mu \text{m}$ source–drain spacing ( $L_{\textrm {SD}})$ , and 0.6- $\mu \text{m}$ gate–drain spacing ( $L_{\textrm {GD}})$ were fabricated and characterized. Devices were observed to hold a gate-to-drain voltage of 230 V in the OFF-state. The gate-to-drain electric field corresponds to 3.8 MV/cm, which is the highest reported for any transistor and surpassing bulk GaN and SiC theoretical limits. Further performance projections are made based on layout, process, and material optimizations to be considered in future iterations.

SECTION I. Introduction

Interest in $\beta $ -Ga₂O₃ as the next generation power semiconductor has grown quickly due to its potential in high power switching supported by the high critical field strength about 8 MV/cm ($\text{E}_{\mathrm {c}})$ as a result of the 4.8 eV bandgap [1]–​[6]. For low conduction loss, minimizing the on-state resistance ($R_{\textit{ON}})$ and maximizing operating voltage are key as described by Baliga [7]. The combination of projected breakdown field and mobility gives $\beta $ -Ga₂O₃ a $V_{\textit{BK}}^{2}/R_{\textit{ONSP}}$ Figure of merit (FOM) of 34,000 MW/cm2, where $V_{\textit{BK}}$ and $R_{\textit{ONSP}}$ are breakdown voltage and on-resistance normalized for device area. $\beta $ -Ga₂O₃ devices with electron mobility values near 100 cm²/$\text {V}\cdot \text {s}$ at 300K have been reported in the literature [8], [9]. High blocking voltages approaching 0.75 kV have also be demonstrated [6]. However, due to the very early stage of the development, the advantage of $V_{\textit{BK}}^{2}/R_{\textit{ONSP}}$ FOM was not shown. In this work, we report a $\beta $ -Ga₂O₃ metal-oxide semiconductor field effect transistor (MOSFET) with record observed gate-to-drain electric field strength >3.8 MV/cm ($V_{\textit{BK}}/L_{\textit{GD}})$ . Although not reaching the theoretical limit, this is the highest field strength measured in a transistor surpassing theoretical bulk critical field strengths for GaN (3 MV/cm) and SiC (3.18 MV/cm).

SECTION II. Material Growth and Device Fabrication

Sn-doped $\beta $ -Ga₂O₃ was homoepitaxially grown by metal-organic vapor phase epitaxy (MOVPE) on a Mg-doped (100) $\beta $ -Ga₂O₃ single crystal substrate. The substrate was cut from a two-inch boule grown via the Czochralski method [10]. The 200-nm epitaxial layer was doped with Sn donor concentration of 1.7E18 cm$^{\mathrm {-3}}$ measured by CV as-grown [11]. Device isolation was performed with an ICP/RIE etch using BCl₃ chemistry. Source-drain electrodes were formed using evaporated Ti/Al/Ni/Au (20/100/50/50 nm) metals and observed to be ohmic after annealing for 60 s in a nitrogen ambient at 470 °C as described by Higashiwaki et al. [2]. A blanket 20-nm thick Al₂O₃ layer was deposited by atomic layer deposition which served as both the gate oxide and channel passivation. Al₂O₃ was removed in the ohmic regions using a buffered oxide etch. Finally, interconnect and gate metal were patterned and deposited simultaneously using a 20/480 nm Ti/Au metal stack. The post-processed carrier concentration was measured via Hall Effect to be 4.8E17 cm$^{\mathrm {-3}}$ after the ohmic contact anneal. A representative two-finger MOSFET can be seen in Fig. 1 with $L_{G}=2~\mu \text{m}$ , $L_{\textit{GS}}=0.8~\mu \text{m}$ , and $L_{\textit{GD}}=0.6~\mu \text{m}$ which were verified by scanning electron microscopy (SEM).

Fig. 1.

(a) Top-down SEM image of the $2\times 50~\mu \text{m}~\beta $ -Ga₂O₃ MOSFET with $L_{G}= 2~\mu \text{m}$ , $L_{\textit{GS}}= 0.8~\mu \text{m}$ , and $L_{\textit{GD}}= 0.6~\mu \text{m}$ . (b) Angled view SEM image of the gate finger. (c) Cross-sectional SEM view of the source-drain space and gate finger.

SECTION III. DC Measurements

Standard DC I-V measurements were made with ground-signal-ground probes on a Cascade automated test station with a slight overpressure of nitrogen. Fig. 2 shows transfer characteristics for several FETs taken at $V_{DS}= 10$ V. The $I_{\textit{ON}}/ I_{\textit{OFF}}$ ratio was measured as high as $10^{7}$ . The pinch-off voltage is defined by a drain current density of 100 nA/mm. We typically observe a pinch-off voltage around −30 V. The devices show a broad peak $g_{m}$ . The maximum drain current ($I_{\textit{DS}})$ typically is around 60 mA/mm.

Fig. 2.

Current density (left) and transconductance (right) are shown for multiple devices. The transfer characteristics were taken at a drain voltage of 10 V. $I_{\textit{ON}} / I_{\textit{OFF}}$ ratios are as high as $10^{7}$ . The transconductance shows a broad peak across $\sim 15$ V. The shapes for current density and transconductance correlate with the same device.

Fig. 3 shows the DC family of output curves for an FET from $V_{\textit{GS}}= \,\, 0$ to $V_{\textit{GS}}= \,\, -30$ V with a gate step of −2 V. Positive gate bias was found to degrade the devices and was avoided. This is consistent with observations of trap assisted tunneling through an Al₂O₃ gate dielectric as reported by Hung et al. [12]. The output curves were power limited at 10 mW to avoid thermally induced degradation. The inset of Fig. 3 shows gate and drain leakage in the pinch off condition of −30 V on the gate. Van der Pauw test structures were used to measure average mobility and sheet resistance values of 19.7 ± 1.5 cm²/$\text {V}\cdot \text {s}$ and $33 \pm 3.7~\text{k}\Omega $ /□ via the Hall Effect. Contact resistance ($R_{C})$ was calculated to be $16~\Omega \cdot \text {mm} $ by subtracting the channel resistance from $R_{\textit{ON}}$ . This value correlates with circular transfer length measurements (TLM).

Fig. 3.

Family of output curves for a $2\times 50~ \mu \text{m}$ MOSFET. The gate bias starts at 0 V (black) and pinches off at −30 V (red). The I-V curves were power limited at 10 mW. The inset shows drain (solid) and gate (dashed) current in the pinch-off condition of −30 V.

Three-terminal breakdown tests were conducted by sweeping $V_{\textit{DS}}$ up to 200 V with $V_{\textit{GS}}= -30$ V without catastrophic breakdown. A lower bound on the maximum field strength of 3.8 MV/cm is calculated using a linear electric field gradient approximation for a $V_{\textit{GD}}= - 230$ V potential difference across $0.6~\mu \text{m}$ gate-drain separation. Repeated high voltage drain sweeps induced catastrophic gate dielectric breakdown as evidenced by orders of magnitude increase in gate current. We believe with improved dielectric optimization, we will be able to extend the breakdown strength.

SECTION IV. Simulation

Sentaurus Device simulation of drift-diffusion electron transport was performed to validate the maximum field strength observed experimentally at the $\beta $ -Ga2O3 epitaxial layer/dielectric interface under high voltage pinch-off conditions.

The device mesh was constructed to match our fabricated MOSFET geometry. Fig. 4(a) shows a contour plot of the device cross section ranging from the measured gate ($\text {VGS} =- 30$ V) and drain ($\text {VDS} = 200$ V) bias. The gate footprint and sidewall slope was matched against the SEM cross section in Fig. 1(c). The Ga2O3 epitaxial layer was modeled as Nd - Na = 4.8E17 cm-3 to reflect the post-processing observed carrier concentration. A mid-gap acceptor state concentration of 4.0E17 cm-3 was assumed to be in the semi-insulating $\beta $ -Ga2O3 substrate. The peak field was found to be a significant function of epitaxy and substrate doping/trap concentrations. The mean field was a modest function of these. The unknowns were set at conservative values (lower doping/trap concentration) to project the lower bound on values for average and peak electric field. The simulated potential is plotted against position in Fig. 4(b). The slope of this plot gives the electric field strength. The average and maximum field strength experienced by the $\beta $ -Ga2O3 (at the dielectric semiconductor interface) is calculated to be 3.5 MV/cm (red) and 5.3 MV/cm (black) respectively. The averaged simulated field strength agrees closely with our measured breakdown strength of 3.8 MV/cm, which is an improvement by a factor of 7 with respect to the most recent $\beta $ -Ga₂O₃ publication of 0.54 MV/cm [6]. This improvement is due to our much smaller gate-drain spacing, for which we observe the lateral electric field is fairly uniform in magnitude. This allows the averaged result to more accurately reflect the true peak electric field. In contrast, in the limit of vary large gate-drain spacing, the average field will approach zero while the peak lateral field will be determined by the size of the depletion region.

Fig. 4.

(a) Simulation of the electrostatic potential. The full simulation domain (not shown) included the full channel region and $> \,\, 100~\mu \text{m}$ of substrate to capture the full electrically active region. The curved black lines are equipotential contours. The bold black line is the substrate/epitaxy interface. The epitaxy/dielectric interface is denoted by the black and white dashed line. (b) The simulated electrostatic potential is plotted against position along the semiconductor-oxide interface (black and white dashed line). This is where breakdown is expected to occur. The potential slope is equal to the field strength across the drift region. The average field is calculated to be 3.5 MV/cm (red line), with a maximum of 5.3 MV/cm.

SECTION V. Benchmarking

Power semiconductor device efficiency is a function of $R_{\textit{ON}}$ and $V_{\textit{BK}}$ . Baliga [13] derived a figure of merit for vertical unipolar devices that predicts $R_{\textit{ON}}$ as a function of breakdown voltage for an arbitrary semiconductor material technology. This relationship can be seen in (1) below:\begin{equation} R_{\textit{ONSP}}=\frac {4V_{\textit{BK}}^{2}}{(\varepsilon \cdot \mu \cdot E_{C}^{3})} \end{equation} where $\varepsilon $ is the dielectric constant, $\mu $ is the mobility, and $E_{c}$ is the critical field strength. Plotting $R_{\textit{ONSP}}$ versus $V_{\textit{BK}}$ gives a theoretical BFOM limit for a particular material technology. We report an $R_{\textit{ONSP}}$ of 4.86 $\text{m}\Omega \cdot \text {cm}^{2}$ by normalizing measured $R_{\textit{ON}}$ (at $V_{\textit{GS}}= 0$ ) multiplied by the device area ($L_{SD}\cdot W_{G})$ according to Amato [14]. The results are plotted for the maximum observed blocking voltage at $V_{\textit{GD}}= - 230$ V in Fig. 5 and compared against maximum theoretical power performance for Si, GaN, and $\beta $ -Ga₂O₃. Material constants were taken from [1]. State-of-the-art lateral $\beta $ -Ga₂O₃ and GaN devices were also plotted using red hexagons and green squares for comparison [15]–​[20].

Fig. 5.

Theoretical limits for $R_{\textit{ONSP}}$ vs. $V_{B}$ for Si, GaN, and $\beta $ - Ga₂O₃ are plotted using (1). The filled red star represents this work. The open stars are projections based on layout adjustments and optimization of $R_{C} E_{c}$ . The dashed lines represent BFOMs for a given mobility. If the mobility reaches bulk values in the low doping limit, the second dashed line would be reached. The green squares are state-of-the-art lateral GaN devices.

A power figure of merit ($V_{\textit{BK}}^{2}/R_{\textit{ONSP}})$ of 11 MW/cm² is calculated from the measured data for our un-optimized device. In this device, $R_{C}$ accounts for 22% of $R_{\textit{ON}}$ . Performance improvements are achievable through contact resistance reduction to achieve the top open star in Fig. 5 by using an ohmic implant process as demonstrated in [2]. Further improvements to $R_{\textit{ON}}$ by reducing parasitic access resistance are achievable through gate scaling and self-aligned source contacts. In the limit of a highly scaled gate process with self-aligned source contacts, this translates to $\sim 5$ /6 of the channel resistance being removed for our device by removing 0.8 $\mu \text{m}$ of source-to-gate access resistance and almost $2.0~\mu \text{m}$ of access resistance through the gate region in a $3.4~\mu \text{m}$ channel. $R_{\textit{ON}}$ was calculated with the excess sheet resistance removed to project device performance of a short-channel, self-aligned structure. This is noted in Fig. 5 using the bottom open red star. Further optimization is expected through realization of the full 8 MV/cm critical field strength of $\beta $ -Ga₂O₃ compared to our experimentally observed 3.8 MV/cm. In this case, a $V_{\textit{BK}}^{2}/R_{\textit{ONSP}}$ of 1,600 MW/cm² could be realized (top dashed line). Optimization of the mobility toward the projected bulk mobility of 300 cm²/Vs [4] will increase the figure of merit to 24,000 MW/cm² (bottom dashed line). The discrepancy between the bottom dashed line and theoretical limit arise from the finite contact resistance assumption used and not operating the reported device at positive $\text{V}_{\mathrm {\textit{GS}}}$ to achieve minimum $\text{R}_{\mathrm {\textit{ON}}}$ .

SECTION VI. Conclusions

A two-finger MOSFET was fabricated on a Sn-doped $\beta $ -Ga₂O₃ epitaxial layer, which was grown on a Mg-doped semi-insulating bulk (100) $\beta $ -Ga₂O₃ substrate via MOVPE. Standard DC I-V characterization was performed yielding a pinch-off voltage of −30 V giving an $I_{\it ON/OFF}$ ratio of $10^{7}$ . Hall Effect measurements show a mobility and sheet resistance of 19.7 cm²/Vs and 33k$\Omega $ /□. The MOSFET was found to have a $V_{\textit{BK}}^{2}/R_{\textit{ONSP}}$ of 11 MW/cm². An ideal device with minimal access region and contact resistance would reduce the $R_{\textit{ON}}\cdot A$ product by 97%. Removing these parasitic contributions and achieving maximum $\mu $ and $E_{C}$ gives a $V_{\textit{BK}}^{2}/R_{\textit{ONSP}}$ of 24,000 MW/cm². A family of output curves was recorded with gate dielectric breakdown occurring at a total gate-to-drain voltage of −230 V. This gives a measured semiconductor field strength of 3.8 MV/cm. Sentaurus Device was used to verify this strength and calculates a lower bound for the average and maximum field strength of 3.5 MV/cm and 5.3 MV/cm respectively, across the drift region at the semiconductor/dielectric interface. This is the highest measured electric field strength in a lateral transistor surpassing theoretical limits of bulk SiC and GaN.