10.5-14.5GHz four-channel phased array receiver in 0.13-μm CMOS technology

This paper presents the design of a fully integrated CMOS 4-channel phased-array receiver for 10.5-14.5 GHz telecom infrastructure, microwave link and radar applications. The phased-array is built using 0.13μm CMOS, and has a gain of 24.5 dB at 12.5 GHz, an input IIP3 of -7.3 dBm, a NF of 4.8 dB and the RMS phase error is 3o. The chip occupies an area of 2.9×3.2mm with a total power consumption of 204 mW from a 1.5-V supply. This paper presents the design of all the receiver blocks; LNA, phase shifter, combiner and the I/Q mixer, and finally the layout of the full chip and post layout verification and electromagnetic simulations of entire chip are presented. The design and simulations are carried out using different CAD tools like Cadence, ADS and Sonnet.

I. Introduction

Phased arrays employ a group of antennas in which the relati ve phases of the signals feeding the antennas are varied in such a way that the total radiation pattern is reinforced in a desired direction and suppressed in undesired directions, early phased-array electronics were developed with a hybrid-designs in which packaged transistors, stand-alone phase shifter, switches and passive components are assembled together on a ceramic board, resulting in high cost and large area. By leveraging silicon technologies and adopting commercial IC processes, highly reliable and low-cost phased-arrays can be designed. Eventually silicon technologies will allow integrating all the phased-arrays including RF, analog and digital blocks, into a single chip.