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Mohamed Mobarak - IEEE Xplore Author Profile

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Multiple-input multiple-output (MIMO) wireless communication systems are susceptible to the intermodulation of the multiple signals received and strong blockers, neces-sitating high in-band and out-of-band (OOB) linearity. This work introduces a mixer-first front-end architecture that in-corporates a trans-impedance amplifier (TIA) with a capacitive positive feedback technique to leverage second-o...Show More
Digital phase-locked loops (DPLLs) based on bang-bang phase detectors (BBPD) are now very common in many communication systems specially in clock and data recovery. However, it suffers from long settling time due to cycle slipping issue and even at some point it fails to achieve lock. This paper presents a simple and efficient technique to resolve the issue of locking failure in bang-bang phase-lo...Show More
The continuous development of modern wireless communication technologies has necessitated the development of highly efficient power amplifiers (PAs) for 5G NR applications. This paper presents a comparative study of parallel and series configurations of the Doherty mm-wave PA implemented in Global Foundries 22-nm SOI FDX process. Both configurations aim to enhance Power Back-Off (PBO) efficiency, ...Show More
This letter proposes an error vector magnitude (EVM) modeling and analysis approach for a 5G mm-wave device under test IC (DUT). This model incorporates the signal characteristics (e.g., bandwidth (BW), peak-to-average-power ratio (PAPR), and power level) and the system characteristics (e.g., intermodulation distortion (IMD) and amplitude modulation (AM–AM) $\ldots $ ). The proposed approach accur...Show More
This paper presents a Doherty power amplifier (PA) architecture to improve the power back-off (PBO) efficiency at millimeter-wave (mm-Wave) frequencies by utilizing a novel power combining technique that reduces the losses at the output combining network. The architecture is applied to the transformer-based Doherty for its low area footprint and its balun operation. The proposed PA is designed and...Show More
This paper presents a 24-44 GHz wideband highly linear and efficient class-AB 2-stacked power amplifier (PA) in 65-nm bulk CMOS process for 5G phased array applications. To boost the output power (POUT) and power added efficiency (PAE) a differential 2-stacked transistors with a higher supply (2V) is used. Cross-Coupled neutralization capacitors and shunt inductors are used at the intermediate nod...Show More
This paper presents a wideband low-noise amplifier (LNA) for 5G applications operating from 24 to 41.5 GHz. The LNA consumes 42.6 mA from 1.2 V supply. A conventional diode connected linearization transistor was used to enhance the third-order input intercept point (IIP3) without improving the input 1dB compression point (IP1dB). A new technique to enhance the IP1dB to improve the LNA input dynami...Show More
In this paper, a wide band high linearity 65-nm CMOS Variable Gain Amplifier (VGA) for millimeter-wave (mm-wave) 5G communications is presented. The VGA achieves 14 dB gain range with 1 dB gain step achieved by 9-bit digital gain control. It realizes a maximum phase variation of 2.28o, RMS phase variation of 1.64o and a maximum gain error of 0.28 dB for all gain states across the frequency range. ...Show More
There are many challenges in building millimeter-Wave (mmW) 5G radios [1] –[3]. Some of the key challenges are the cost, heat dissipation, and array calibration. This paper describes ADI’s full line-up of mmW 5G radios used today, with a focus on the millimeter wave front-end portion, and how it addresses some of these challenges. The radio block diagram, shown in Fig. 2.1.1, is an example of a du...Show More
This paper presents the design of CMOS high linearity I/Q mixer for 9-16-GHz down conversion applications. The mixer is built using 0.13μm CMOS, and it has a gain of 3dB, an input IIP3 of 18dBm, a NF of 15.5 dB, The I/Q mixer achieves a Phase balance of 3°, and amplitude balance of 0.3dB. The mixer occupies an area of 1.5×2.3mm with a total power consumption of 45 mW from a 1.5-V supply, and requi...Show More
This paper presents the design of a fully integrated CMOS 4-channel phased-array receiver for 10.5-14.5 GHz telecom infrastructure, microwave link and radar applications. The phased-array is built using 0.13μm CMOS, and has a gain of 24.5 dB at 12.5 GHz, an input IIP3 of -7.3 dBm, a NF of 4.8 dB and the RMS phase error is 3o. The chip occupies an area of 2.9×3.2mm with a total power consumption of...Show More
A highly linear, efficient, two-stage power amplifier for high-data-rate wireless applications is presented. The linearity is greatly improved by adding an auxiliary amplifier to the main bipolar transistor amplifier in a feed-forward approach to cancel out the nonlinearity terms. The efficiency enhancement is achieved using a switchable biasing and a reconfigurable output-matching network based o...Show More
A highly linear, efficient power amplifier for high data rate wireless applications is presented. The linearity is greatly improved by adding an auxiliary amplifier to the main bipolar junction transistor (BJT) in a feed-forward approach to cancel out the non-linearity terms. The efficiency enhancement is achieved using a switchable biasing and output matching network based on the available input ...Show More
An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distor...Show More