An Algorithm Used in a Power Monitor to Mitigate Dark Silicon on VLSI Chip

Data with increasing bandwidth requires future general-purpose as well as application specific microprocessors to improve performance endlessly. Transistor scaling, novel transistor structures, novel state-of-art VLSI design techniques and new computer architectures are the key drivers for boosting power and performance of microprocessors. Unfortunately, the processor cooling technique is unable to keep pace with higher density of transistors and high performance. For appropriate trade-offs between performance and limitation of power dissipation, dark silicon has appeared in the current processors. With the number of transistors increasing in future chips, we could envision that next generation processors might be getting darker and darker. This compromise could reduce multiple-core processors' efficiency. In this paper, power dissipation and circuit optimization are discussed in an attempt to mitigate dark silicon for future processors. A power monitor and its algorithm are proposed mainly to explain how to efficiently regulate voltage and power in the future processors with multiple cores.

I. Introduction

Down scaling of transistors promotes high density of transistors in a microprocessor design. Meanwhile in last 20 years, clock frequency as well as the required LAN bandwidth LAN increased significantly due to the development of advanced communication technology [1]. Dark silicon, which refers to a part of transistors in a chip which drops work frequency and compromises with the limitation of cooling technique, increases in a chip [2]. Dark silicon largely occupies the entire chip and seriously influences work performance of processors, especially in advanced multiple-core designs [3]. It can be anticipated that dark silicon will become larger in chip if there is no implementation of novel processor topology as well as invention of state-of-art circuit. Even worse, dark silicon might result in failure of MOS scaling [4].