Analysis, Design, and Prototyping of Temperature Resilient Clock Distribution Networks for 3-D ICs

The 3-D integrated circuits (3-D ICs) overcome the bottlenecks in system performance and circuit density. However, their increased power and thermal density cause temperature gradients in the chip that significantly affect signal and power integrity. Temperature gradients significantly degrade the clock signal, a key signal in digital systems, which in turn degrades system performance. In this paper, we investigate the effect of thermal gradients on the clock distribution network in the 3-D ICs along with the power distribution network. We also present power-efficient compensation methods for minimizing temperature-induced skew using the thermoelectrical analysis and use them to design a custom IC in which we compare the skew, the power, and the area. Finally, using measurements, we validate the design with a field-programmable gate array-based test vehicle.

I. Introduction

3-D integrated circuits (3-D ICs) have many advantages, such as enhanced density, improved electrical performance, and efficient power [1]. However, the 3-D technology has raised several issues in modeling, design, fabrication, testing, and thermal management. One of the most critical problems in recent 3-D systems, similar to other deep submicron technologies, is temperature-induced problems resulting from increased power density in 3-D ICs [2]. Temperature gradients caused by hot spots in 3-D ICs are three times more severe than the conventional ICs [3]. Some systems have shown high on-chip temperature gradients of over 50 °C [4], leading to significant problems [5].